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march 1998 1/72 r rev. 2.3 st62t45b/e45b 8-bit otp/eprom mcu with lcd driver, eeprom and a/d converter n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +85 c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 128 bytes n data eeprom: 128 bytes n user programmable options n 19 i/o pins, fully programmable as: input with pull-up resistor input without pull-up resistor input with interrupt generation open-drain or push-pull output analog input lcd segments (8 combiport lines) n 4 i/o lines can sink up to 20ma to drive leds or triacs directly n two 8-bit timer/counter with 7-bit programmable prescaler n digital watchdog n 8-bit a/d converter with 7 analog inputs n 8-bit synchronous peripheral interface (spi) n lcd driver with 24 segment outputs, 4 backplane outputs and selectable multiplexing ratio. n 32khz oscillator for stand-by lcd operation n on-chip clock oscillator can be driven by quartz crystal or ceramic resonator n one external non-maskable interrupt n st6245-emu2 emulation and development system (connects to an ms-dos pc via a parallel port). device summary (see end of datasheet for ordering information) pqfp52 cqfp52w device otp (bytes) eprom (bytes) i/o pins st62t45b 3884 - 11 to 19 ST62E45B 3884 11 to 19 1
2/72 table of contents 72 2 st62t45b/e45b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 general description . . . . . . . ...............................................5 1.1 introduction .........................................................5 1.2 pin descriptions . . . . . . . . . . ............................................7 1.3 memorymap ..........................................................8 1.3.1 introduction . . . . . . . . ................................................8 1.3.2 program space . . . . . . . . . . . . . . . . . . . . . . . . . . . ..........................9 1.3.3 data space . . . . . . . . ...............................................10 1.3.4 stack space . . . . . . . . . . . . . . . . . ......................................10 1.3.5 data window register (dwr) . . . . . . . . . . . . . . . . . . . . .....................11 1.3.6 data ram/eeprom bank register (drbr) ..............................12 1.3.7 eeprom description ...............................................13 1.4 programming modes .................................................15 1.4.1 option byte . . . . . . . . ...............................................15 1.4.2 program memory . . . . ...............................................15 1.4.3 eeprom data memory . . . . . . . . . . . . ..................................15 1.4.4 epromerasing....................................................15 2 central processing unit .................................................16 2.1 introduction ........................................................16 2.2 cpu registers . . . . . . . . ...............................................16 3 clocks, reset, interrupts and power saving modes . . . . . . . ..............18 3.1 clocksystem........................................................18 3.1.1 main oscillator . . . . . . . . . . ...........................................18 3.1.2 32khz stand-by oscillator ......................................19 3.2 resets...............................................................20 3.2.1 reset input ......................................................20 3.2.2 power-on reset . . . . . . . . . . . . . . . .....................................20 3.2.3 watchdog reset . . . . ...............................................21 3.2.4 application notes . . . . ...............................................21 3.2.5 mcu initialization sequence ..........................................21 3.3 digital watchdog . . . . . . . . . . . . . . . .....................................23 3.3.1 digital watchdog register (dwdr) . . . ..................................25 3.3.2 application notes . . . . ...............................................25 3.4 interrupts . . . . ......................................................27 3.4.1 interrupt request . . . . . . . . . . . . . . . .....................................27 3.4.2 interrupt procedure . . . ..............................................28 3.4.3 interrupt option register (ior) . . . . ....................................29 3.4.4 interrupt sources . . . . ...............................................29 3.5 power saving modes .................................................31 3.5.1 wait mode . . . . . . . . ...............................................31 3.5.2 stopmode .......................................................31 3.5.3 exit from wait and stop modes . . . ...................................32
3/72 table of contents 3 4 on-chip peripherals . . . ...................................................33 4.1 i/oports.............................................................33 4.1.1 operating modes . . . . ...............................................34 4.1.2 safe i/o state switching sequence . . . ..................................35 4.1.3 lcd alternate functions (combiports) ...................................37 4.1.4 spi alternate functions . . . ............................................37 4.1.5 i/o port option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................38 4.1.6 i/o port data direction registers . . . ....................................38 4.1.7 i/o port data registers . . . . ..........................................38 4.2 timer1&2............................................................39 4.2.1 timer 1 operating modes . . . . . . .....................................41 4.2.2 timer 2 operating mode . . . . . . . . . . . . . . . . . . . . ........................41 4.2.3 timer interrupt . . . . . . . . . . ...........................................41 4.2.4 application notes . . . . ...............................................41 4.2.5 timer 1 registers . .................................................42 4.2.6 timer 2 registers . .................................................43 4.3 a/d converter (adc) . . . ..............................................44 4.3.1 application notes . . . . ...............................................44 4.4 serial peripheral interface (spi) . . . . . . . . . . . . ........................46 4.5 lcd controller-driver . . . . ..........................................48 4.5.1 multiplexing ratio and frame frequency setting . . . . ........................49 4.5.2 segment and common plates driving. . ..................................49 4.5.3 lcdram.........................................................50 4.5.4 stand by or stop operation mode . . . . . . . . . . ...........................51 4.5.5 lcd mode control register (lcdcr) ...................................51 5software ................................................................52 5.1 st6 architecture . . . . . . . . . . . . . . . .....................................52 5.2 addressing modes . . . . ...............................................52 5.3 instruction set . . . ...................................................53 6 electrical characteristics . . . . . . . . . . . . ..................................58 6.1 absolute maximum ratings . ..........................................58 6.2 recommended operating conditions. . . ..............................59 6.3 dc electrical characteristics ......................................60 6.4 ac electrical characteristics ......................................61 6.5 a/d converter characteristics . . . ...................................61 6.6 timer characteristics . . . ............................................62 6.7 spi characteristics . . . ..............................................62 6.8 lcd electrical characteristics . . . . . . . . . . ...........................62 6.9 pss electrical characteristics (when available) . . . . . . . . . . . . . . . .....62 7 general information . . . . . . . . . . ...........................................63 7.1 package mechanical data . . . . ........................................63 7.2 package thermal characteristic . . ..................................64 7.3 ordering information ...............................................64
4/72 table of contents 72 1 st62p45b . ........................................65 1 general description . . . . . . . ..............................................66 1.1 introduction ........................................................66 1.2 ordering information ...............................................66 1.2.1 transfer of customer code . ..........................................66 1.2.2 listing generation and verification . . . . . . . . . . ...........................66 st6245b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 1 general description . . . . . . . ..............................................70 1.1 introduction ........................................................70 1.2 rom readout protection . . . . . . . . . . . . . . . . . . . . ........................70 1.3 ordering information ...............................................72 1.3.1 transfer of customer code . ..........................................72 1.3.2 listing generation and verification . . . . . . . . . . ...........................72
5/72 st62t45b/e45b 1 general description 1.1 introduction the st62t45b and ST62E45B devices are low cost members of the st62xx 8-bit hcmos family of microcontrollers, which are targeted at low to medium complexity applications. all st62xx de- vices are based on a building block approach: a common core is surrounded by a number of on- chip peripherals. the ST62E45B is the erasable eprom version of the st62t45b device, which may be used to em- ulate the st62t45b device, as well as the respec- tive st6245b rom devices. figure 1. block diagram test nmi interrupt program pc stac k level 1 stac k level 2 stac k level 3 stac k level 4 stac k level 5 stac k level 6 power supply oscillator reset data rom user selectable data ram port a port b timer 1 digita l 8 bit core test/v pp 8-bit a/d converter pa5..pa7/ain v dd v ss oscin oscout reset watc hdog memory port c spi (serial peripheral interface) 12 8 bytes 3884 bytes data eeprom 128 bytes pb0..pb3/ain pc0..pc7/s33..s40 s17..s32 com1..com4 (vpp on eprom/otp versions only) pb4/20ma sink pb5/scl/20ma sink pb6/sin/20ma sink pb7/sout/20ma sink vlcd vlcd1/3 vlcd2/3 osc 32khz timer 2 osc32in osc32out lcd driver vr01994 timer 4
6/72 st62t45b/e45b introduction (cont'd) otp and eprom devices are functionally identi- cal. the rom based versions offer the same func- tionality selecting as rom options the options de- fined in the programmable option byte of the otp/eprom versions.otp devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programma- bility are required. these compact low-cost devices feature two tim- ers comprising an 8-bit counter and a 7-bit pro- grammable prescaler, eeprom data capability, a serial synchronous port interface (spi), an 8-bit a/d converter with 8 analog inputs, a digital watchdog timer, and a complete lcd controller driver, making them well suited for a wide range of automotive, appliance and industrial applications. figure 2. 52 pin qfp package table 1. st6245b pin description * note : 20ma sink 27 14 13 40 52 12 3 39 26 vr01649c pin number pin name pin number pin name pin number pin name pin number pin name 1 com4 14 reset 27 osc32out 40 s28 2 com3 15 oscout 28 osc32in 41 s29 3 com2 16 oscin 29 s17 42 s30 4 com1 17 nmi 30 s18 43 s31 5 vlcd1/ 3 18 timer 31 s19 44 s32 6 vlcd2/ 3 19 pb7/ sout * 32 s20 45 pc0/s33 7 vlcd 20 pb6/ sin* 33 s21 46 pc1/s34 8 pa7/ ain 21 pb5/ scl * 34 s22 47 pc2/s35 9 pa6/ ain 22 pb4 * 35 s23 48 pc3/s36 10 pa5/ ain 23 pb3/ ain 36 s24 49 pc4/s37 11 test 24 pb2/ ain 37 s25 50 pc5/s38 12 vdd 25 pb1/ain 38 s26 51 pc6/s39 13 vss 26 pb0/ain 39 s27 52 pc7/s40 5
7/72 st62t45b/e45b 1.2 pin descriptions v dd and v ss . power is supplied to the mcu via these two pins. v dd is the power connection and v ss is the ground connection. oscin and oscout. these pins are internally connected to the on-chip oscillator circuit. a quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. the oscin pin is the input pin, the oscout pin is the output pin. reset . the active-low reset pin is used to re- start the microcontroller. test/v pp . the test must be held at v ss for nor- mal operation (an internal pull-down resistor se- lects normal operating mode if test pin is not connected). if test pin is connected to a +12.5v level during the reset phase, the eprom/otp programming mode is entered. nmi. the nmi pin provides the capability for asyn- chronous interruption, by applying an external non maskable interrupt to the mcu. the nmi input is falling edge sensitive with schmitt trigger charac- teristics. the user can select as option the availa- bility of an on-chip pull-up at this pin. pa5-pa7. these 3 lines are organised as one i/o port (a). each line may be configured under soft- ware control as input with or without internal pull- up resistors, input with interrupt generation and pull-up resistor, open-drain or push-pull output, or as analog input for the a/d converter. pb0...pb7. these 8 lines are organised as one i/o port (b). each line may be configured under software control as input with or without internal pull-up resistors, input with interrupt generation and pull-up resistor, open-drain or push-pull output, analog input for the a/d converter. pb0..pb3 can be used as analog inputs for the a/d converter , while pb7/sout, pb6/sin and pb5/scl can be used respectively as data out, data in and clock pins for the on-chip spi. in addi- tion, pb4..pb7 can sink 20ma for direct led or triac drive. pc0-pc7 . these 8 lines are organised as one i/o port (c). each line may be configured under soft- ware control as input with or without internal pull- up resistor, input with interrupt generation and pull-up resistor, open-drain or push-pull output, or as lcd segment output s33..s40. com1-com4 . these four pins are the lcd pe- ripheral common outputs. they are the outputs of the on-chip backplane voltage generator which is used for multiplexing the 45 lcd lines allowing up to 180 segments to be driven. s17..s40 . these pins are the 24 lcd peripheral segment outputs. s33..s40 are alternate functions of the port c i/o pins. (combiports feature) vlcd . display voltage supply. it determines the high voltage level on com1-com4 and s4-s48 pins. vlcd1/3, vlcd2/3 . display supply voltage inputs for determining the display voltage levels on com1-com4 and s4-s48 pins during multiplex operation. osc32in and osc32out . these pins are inter- nally connected with the on-chip 32khz oscillator circuit. a 32.768khz quartz crystal can be con- nected between these two pins if it is necessary to provide the lcd stand-by clock and real time in- terrupt. osc32in is the input pin, osc32out is the output pin. timer . this is the timer 1 i/o pin. in input mode, it is connected to the prescaler and acts as external timer clock or as control gate for the in- ternal timer clock. in output mode, the timer pin outputs the data bit when a time-out occurs.the user can select as option the availability of an on- chip pull-up at this pin. 6
8/72 st62t45b/e45b 1.3 memory map 1.3.1 introduction the mcu operates in three separate memory spaces: program space, data space, and stack space. operation in these three memory spaces is described in the following paragraphs. briefly, program space contains user program code in program memory and user vectors; data space contains user data in ram and in program memory, and stack space accommodates six lev- els of stack for subroutine and interrupt service routine nesting. figure 3. memory addressing diagram program space program interrupt & reset vectors accumulator data ram bank select window select ram x register y register v register w register data read-only window ram / eeprom banking area 000h 03fh 040h 07fh 080h 081h 082h 083h 084h 0c0h 0ffh 0-63 data space 0000h 0ff0h 0fffh memory memory data read-only memory vr01568 7
9/72 st62t45b/e45b memory map (cont'd) 1.3.2 program space program space comprises the instructions to be executed, the data required for immediate ad- dressing mode instructions, the reserved factory test area and the user vectors. program space is addressed via the 12-bit program counter register (pc register). 1.3.2.1 program memory protection the program memory in otp or eprom devices can be protected against external readout of memory by selecting the readout protec- tion option in the option byte. in the eprom parts, readout protection option can be disactivated only by u.v. erasure that also results into the whole eprom context erasure. note: once the readout protection is activated, it is no longer possible, even for sgs-thomson, to gain access to the program memory contents. returned parts with a protection set can therefore not be accepted. figure 4. ST62E45B/t45b program memory map 0000h reserved * user program memory (otp/eprom) 3872 bytes 0f9fh 0fa0h 0fefh 0ff0h 0ff7h 0ff8h 0ffbh 0ffch 0ffdh 0ffeh 0fffh reserved * reserved interrupt vectors nmi vector user reset vector 0080h (*) reserved areas should be filled with 0ffh 007fh 8
10/72 st62t45b/e45b memory map (cont'd) 1.3.3 data space data space accommodates all the data necessary for processing the user program. this space com- prises the ram resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in program memory. 1.3.3.1 data rom all read-only data is physically stored in program memory, which also accommodates the program space. the program memory consequently con- tains the program code to be executed, as well as the constants and look-up tables required by the application. the data space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in program memory. 1.3.3.2 data ram/eeprom in st62t45b and ST62E45B devices, the data space includes 60 bytes of ram, the accumulator (a), the indirect registers (x), (y), the short direct registers (v), (w), the i/o port registers, the pe- ripheral data and control registers, the interrupt option register and the data rom window regis- ter (drw register). additional ram and eeprom pages can also be addressed using banks of 64 bytes located be- tween addresses 00h and 3fh. 1.3.4 stack space stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents. table 2. additional ram/eeprom banks. table 3. st62t45b/e45b data memory space device ram eeprom st62t45b/e45b 1 x 64 bytes 2 x 64 bytes data and eeprom 000h 03fh data rom window area 040h 07fh x register 080h y register 081h v register 082h w register 083h data ram 084h 0bfh port a data register 0c0h port b data register 0c1h spi interrupt disable register 0c2h port c data register 0c3h port a direction register 0c4h port b direction register 0c5h port c direction register 0c6h reserved 0c7h interrupt option register 0c8h* data rom window register 0c9h* reserved 0cah* ram/eeprom bank select register 0cbh* port a option register 0cch reserved 0cdh port b option register 0ceh port c option register 0cfh a/d data register 0d0h a/d control register 0d1h timer 1 presc aler register 0d2h timer 1 counter register 0d3h timer 1 status/control register 0d4h timer 2 presc aler register 0d5h timer 2 counter register 0d6h timer 2 status/control register 0d7h watchdog register 0d8h reserved 0d9h reserved 0dah 32khz oscillator control registe r 0dbh lcd mode control register 0dch spi data register 0ddh reserved 0deh eeprom control register 0dfh lcd ram 0e0h 0f7h data ram 0f8h 0feh accumulator offh * write only register 9
11/72 st62t45b/e45b memory map (cont'd) 1.3.5 data window register (dwr) the data read-only memory window is located from address 0040h to address 007fh in data space. it allows direct reading of 64 consecutive bytes located anywhere in program memory, be- tween address 0000h and 1fffh (top memory ad- dress depends on the specific device). all the pro- gram memory can therefore be used to store either instructions or read-only data. indeed, the window can be moved in steps of 64 bytes along the pro- gram memory by writing the appropriate code in the data window register (dwr). the dwr can be addressed like any ram loca- tion in the data space, it is however a write-only register and therefore cannot be accessed using single-bit operations. this register is used to posi- tion the 64-byte read-only data window (from ad- dress 40h to address 7fh of the data space) in program memory in 64-byte steps. the effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the con- tent of the dwr register (as most significant bits), as illustrated in figure 5 below. for instance, when addressing location 0040h of the data space, with 0 loaded in the dwr register, the physical location addressed in program memory is 00h. the dwr register is not cleared on reset, therefore it must be written to prior to the first ac- cess to the data read-only memory window area. data window register (dwr) address: 0c9h e write only bits 7, 6 = not used. bit 5-0 = dwr5-dwr0: data read-only memory window register bits. these are the data read- only memory window bits that correspond to the upper bits of the data read-only memory space. caution: this register is undefined on reset. nei- ther read nor single bit instructions may be used to address this register. note: care is required when handling the dwr register as it is write only. for this reason, the dwr contents should not be changed while exe- cuting an interrupt service routine, as the service routine cannot save and then restore the register's previous contents. if it is impossible to avoid writ- ing to the dwr during the interrupt service rou- tine, an image of the register must be saved in a ram location, and each time the program writes to the dwr, it must also write to the image regis- ter. the image register must be written first so that, if an interrupt occurs between the two instruc- tions, the dwr is not affected. figure 5. data read-only memory window memory addressing 70 - - dwr5 dwr4 dwr3 dwr2 dwr1 dwr0 data rom window register contents data space address 40h-7fh in instruction program space address 765432 0 543210 543210 read 1 6 7 8 9 10 11 0 1 vr01573c 12 1 0 data space address : : 59h 0 0 0 0 1 00 1 1 1 example: (dwr) dwr=28h 11 000 00 00 1 rom address:a19h 11 13 0 1 10
12/72 st62t45b/e45b memory map (cont'd) 1.3.6 data ram/eeprom bank register (drbr) address: cbh e write only bit 7-5 = these bits are not used bit 4 - drbr4 . this bit, when set, selects ram page 2. bit 3 - drbr3 . this bit, when set, selects ram page 1. bit2. these bits are not used. bit 1 - drbr1 . this bit, when set, selects eeprom page 1. bit 0 - drbr0 . this bit, when set, selects eeprom page 0. the selection of the bank is made by program- ming the data ram bank switch register (drbr register) located at address cbh of the data space according to table 1. no more than one bank should be set at a time. the drbr register can be addressed like a ram data space at the address cbh; nevertheless it is a write only register that cannot be accessed with single-bit operations. this register is used to se- lect the desired 64-byte ram/eeprom bank of the data space. the number of banks has to be loaded in the drbr register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3fh address). this register is not cleared during the mcu initial- ization, therefore it must be written before the first access to the data space bank region. refer to the data space description for additional informa- tion. the drbr register is not modified when an interrupt or a subroutine occurs. notes : care is required when handling the drbr register as it is write only. for this reason, it is not allowed to change the drbr contents while executing in- terrupt service routine, as the service routine can- not save and then restore its previous content. if it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a ram location, and each time the program writes to drbr it must write also to the image register. the image register must be written first, so if an interrupt occurs between the two instructions the drbr is not affected. in drbr register, only 1 bit must be set. other- wise two or more pages are enabled in parallel, producing errors. table 4. data ram bank register set-up 70 - - - drbr4 drbr3 - drbr1 drbr0 drbr st62t45b/e45b 00h none 01h eeprom page 0 02h eeprom page 1 08h not available 10h ram page 2 other reserved 11
13/72 st62t45b/e45b memory map (cont'd) 1.3.7 eeprom description eeprom memory is located in 64-byte pages in data space. this memory may be used by the user program for non-volatile data storage. data space from 00h to 3fh is paged as described in table 5. eeprom locations are accessed di- rectly by addressing these paged sections of data space. the eeprom does not require dedicated instruc- tions for read or write access. once selected via the data ram bank register, the active eeprom page is controlled by the eeprom control regis- ter (eectl), which is described below. bit e20ff of the eectl register must be reset prior to any write or read access to the eeprom. if no bank has been selected, or if e2off is set, any ac- cess is meaningless. programming must be enabled by setting the e2ena bit of the eectl register. the e2busy bit of the eectl register is set when the eeprom is performing a programming cycle. any access to the eeprom when e2busy is set is meaningless. provided e2off and e2busy are reset, an eep- rom location is read just like any other data loca- tion, also in terms of access time. writing to the eeprom may be carried out in two modes: byte mode (bmode) and parallel mode (pmode). in bmode, one byte is accessed at a time, while in pmode up to 8 bytes in the same row are programmed simultaneously (with conse- quent speed and power consumption advantages, the latter being particularly important in battery powered circuits). general notes : data should be written directly to the intended ad- dress in eeprom space. there is no buffer mem- ory between data ram and the eeprom space. when the eeprom is busy (e2busy = a1o) eectl cannot be accessed in write mode, it is only possible to read the status of e2busy. this implies that as long as the eeprom is busy, it is not possible to change the status of the eeprom control register. eectl bits 4 and 5 are reserved and must never be set. care is required when dealing with the eectl reg- ister, as some bits are write only. for this reason, the eectl contents must not be altered while ex- ecuting an interrupt service routine. if it is impossible to avoid writing to this register within an interrupt service routine, an image of the register must be saved in a ram location, and each time the program writes to eectl it must also write to the image register. the image regis- ter must be written to first so that, if an interrupt oc- curs between the two instructions, the eectl will not be affected. table 5. row arrangement for parallel writing of eeprom locations dataspace addresses. banks 0 and 1. byte 01234567 row7 38h-3fh row6 30h-37h row5 28h-2fh row4 20h-27h row3 18h-1fh row2 10h-17h row1 08h-0fh row0 00h-07h up to 8 bytes in each row may be programmed simultaneously in parallel write mode. the number of available 64-byte banks (1 or 2) is device dependent. 12
14/72 st62t45b/e45b memory map (cont'd) additional notes on parallel mode: if the user wishes to perform parallel program- ming, the first step should be to set the e2par2 bit. from this time on, the eeprom will be ad- dressed in write mode, the row address will be latched and it will be possible to change it only at the end of the programming cycle, or by resetting e2par2 without programming the eeprom. af- ter the row address is latched, the mcu can only aseeo the selected eeprom row and any attempt to write or read other rows will produce errors. the eeprom should not be read while e2par2 is set. as soon as the e2par2 bit is set, the 8 volatile row latches are cleared. from this moment on, the user can load data in all or in part of the row. setting e2par1 will modify the eeprom regis- ters corresponding to the row latches accessed after e2par2. for example, if the software sets e2par2 and accesses the eeprom by writing to addresses 18h, 1ah and 1bh, and then sets e2par1, these three registers will be modified si- multaneously; the remaining bytes in the row will be unaffected. note that e2par2 is internally reset at the end of the programming cycle. this implies that the user must set the e2par2 bit between two parallel pro- gramming cycles. note that if the user tries to set e2par1 while e2par2 is not set, there will be no programming cycle and the e2par1 bit will be un- affected. consequently, the e2par1 bit cannot be set if e2ena is low. the e2par1 bit can be set by the user, only if the e2ena and e2par2 bits are also set. eeprom control register (eectl) address: dfh e read/write reset status: 00h bit 7 = d7 : unused. bit 6 = e2off : stand-by enable bit. write only. if this bit is set the eeprom is disabled (any access will be meaningless) and the power consumption of the eeprom is reduced to its lowest value. bit 5-4 = d5-d4 : reserved. must be kept reset. bit 3 = e2par1 : parallel start bit. write only. once in parallel mode, as soon as the user software sets the e2par1 bit, parallel writing of the 8 adja- cent registers will start. this bit is internally reset at the end of the programming procedure. note that less than 8 bytes can be written if required, the un- defined bytes being unaffected by the parallel pro- gramming cycle; this is explained in greater detail in the additional notes on parallel mode overleaf. bit 2 = e2par2 : parallel mode en. bit. write only. this bit must be set by the user program in order to perform parallel programming. if e2par2 is set and the parallel start bit (e2par1) is reset, up to 8 adjacent bytes can be written simultane- ously. these 8 adjacent bytes are considered as a row, whose address lines a7, a6, a5, a4, a3 are fixed while a2, a1 and a0 are the changing bits, as illustrated in figure 5. e2par2 is automatically reset at the end of any parallel programming pro- cedure. it can be reset by the user software before starting the programming procedure, thus leaving the eeprom registers unchanged. bit 1 = e2busy : eeprom busy bit. read on- ly. this bit is automatically set by the eeprom control logic when the eeprom is in program- ming mode. the user program should test it be- fore any eeprom read or write operation; any at- tempt to access the eeprom while the busy bit is set will be aborted and the writing procedure in progress will be completed. bit 0 = e2ena : eeprom enable bit. write on- ly. this bit enables programming of the eeprom cells. it must be set before any write to the eep- rom register. any attempt to write to the eep- rom when e2ena is low is meaningless and will not trigger a write cycle. caution: this register is undefined on reset. nei- ther read nor single bit instructions may be used to address this register. 70 d7 e2off d5 d4 e2par1 e2par2 e2busy e2ena 13
15/72 st62t45b/e45b 1.4 programming modes 1.4.1 option byte the option byte allows configuration capability to the mcus. option byte's content is automatically read, and the selected options enabled, when the chip reset is activated. it can only be accessed during the programming mode. this access is made either automatically (copy from a master device) or by selecting the option byte programming mode of the programmer. the option byte is located in a non-user map. no address has to be specified. eprom code option byte bit 7. reserved. bit 6 = nmi pull . . this bit must be set high to re- move the nmi pin pull up resistor when it is low, a pull up is provided. bit 5 = protect . this bit allows the protection of the software contents against piracy. when the bit protect is set high, readout of the otp con- tents is prevented by hardware. no programming equipment is able to gain access to the user pro- gram. when this bit is low, the user program can be read. bit 4. reserved. bit 3 = wdact . this bit controls the watchdog ac- tivation. when it is high, hardware activation is se- lected. the software activation is selected when wdact is low. bit 2 = tim pull. this bit must be set high to con- figure the tim pin with a pull up resistor when it is low, no pull up is provided. bit 1-0 = reserved. the option byte is written during programming ei- ther by using the pc menu (pc driven mode) or automatically (stand-alone mode) 1.4.2 program memory eprom/otp programming mode is set by a +12.5v voltage applied to the test/v pp pin. the programming flow of the st62t45b/e45b is de- scribed in the user manual of the eprom pro- gramming board. the mcus can be programmed with the st62e4xb eprom programming tools available from sgs-thomson. 1.4.3 eeprom data memory eeprom data pages are supplied in the virgin state ffh. partial or total programming of eep- rom data memory can be performed either through the application software, or through an ex- ternal programmer. any sgs-thomson tool used for the program memory (otp/eprom) can also be used to program the eeprom data mem- ory. 1.4.4 eprom erasing the eprom of the windowed package of the mcus may be erased by exposure to ultra violet light. the erasure characteristic of the mcus is such that erasure begins when the memory is ex- posed to light with a wave lengths shorter than ap- proximately 4000?. it should be noted that sun- lights and some types of fluorescent lamps have wavelengths in the range 3000-4000?. it is thus recommended that the window of the mcus packages be covered by an opaque label to prevent unintentional erasure problems when test- ing the application in such an environment. the recommended erasure procedure of the mcus eprom is the exposure to short wave ul- traviolet light which have a wave-length 2537a. the integrated dose (i.e. u.v. intensity x exposure time) for erasure should be a minimum of 15w- sec/cm 2 . the erasure time with this dosage is ap- proximately 15 to 20 minutes using an ultraviolet lamp with 12000 m w/cm 2 power rating. the ST62E45B should be placed within 2.5cm (1inch) of the lamp tubes during erasure. 70 - nmi pull pro- tect - wdact tim pull -- 14
16/72 st62t45b/e45b 2 central processing unit 2.1 introduction the cpu core of st6 devices is independent of the i/o or memory configuration. as such, it may be thought of as an independent central processor communicating with on-chip i/o, memory and pe- ripherals via internal address, data, and control buses. in-core communication is arranged as shown in figure 6; the controller being externally linked to both the reset and oscillator circuits, while the core is linked to the dedicated on-chip pe- ripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers. 2.2 cpu registers the st6 family cpu core features six registers and three pairs of flags available to the programmer. these are described in the following paragraphs. accumulator (a) . the accumulator is an 8-bit general purpose register used in all arithmetic cal- culations, logical operations, and data manipula- tions. the accumulator can be addressed in data space as a ram location at address ffh. thus the st6 can manipulate the accumulator just like any other register in data space. indirect registers (x, y). these two indirect reg- isters are used as pointers to memory locations in data space. they are used in the register-indirect addressing mode. these registers can be ad- dressed in the data space as ram locations at ad- dresses 80h (x) and 81h (y). they can also be ac- cessed with the direct, short direct, or bit direct ad- dressing modes. accordingly, the st6 instruction set can use the indirect registers as any other reg- ister of the data space. short direct registers (v, w). these two regis- ters are used to save a byte in short direct ad- dressing mode. they can be addressed in data space as ram locations at addresses 82h (v) and 83h (w). they can also be accessed using the di- rect and bit direct addressing modes. thus, the st6 instruction set can use the short direct regis- ters as any other register of the data space. program counter (pc). the program counter is a 12-bit register which contains the address of the next rom location to be processed by the core. this rom location may be an opcode, an oper- and, or the address of an operand. the 12-bit length allows the direct addressing of 4096 bytes in program space. figure 6. st6 core block diagram program reset opcode flag values 2 controller flags alu a-data b-data address/read line data space interrup ts data ram/ee prom data rom/eprom results to data space (write line) rom/eprom dedication s accumulator control signals oscin oscout address decoder 256 12 program counter and 6 layer stack 0,01 to 8mhz vr01811 15
17/72 st62t45b/e45b cpu registers (cont'd) however, if the program space contains more than 4096 bytes, the additional memory in pro- gram space can be addressed by using the pro- gram bank switch register. the pc value is incremented after reading the ad- dress of the current instruction. to execute rela- tive jumps, the pc and the offset are shifted through the alu, where they are added; the result is then shifted back into the pc. the program counter can be changed in the following ways: - jp (jump) instructionpc=jump address - call instructionpc= call address - relative branch instruction.pc= pc +/- offset - interrupt pc=interrupt vector - reset pc= reset vector - ret & reti instructionspc= pop (stack) - normal instructionpc= pc + 1 flags (c, z) . the st6 cpu includes three pairs of flags (carry and zero), each pair being associated with one of the three normal modes of operation: normal mode, interrupt mode and non maskable interrupt mode. each pair consists of a carry flag and a zero flag. one pair (cn, zn) is used during normal operation, another pair is used dur- ing interrupt mode (ci, zi), and a third pair is used in the non maskable interrupt mode (cnmi, zn- mi). the st6 cpu uses the pair of flags associated with the current mode: as soon as an interrupt (or a non maskable interrupt) is generated, the st6 cpu uses the interrupt flags (resp. the nmi flags) instead of the normal flags. when the reti in- struction is executed, the previously used set of flags is restored. it should be noted that each flag set can only be addressed in its own context (non maskable interrupt, normal interrupt or main rou- tine). the flags are not cleared during context switching and thus retain their status. the carry flag is set when a carry or a borrow oc- curs during arithmetic operations; otherwise it is cleared. the carry flag is also set to the value of the bit tested in a bit test instruction; it also partic- ipates in the rotate left instruction. the zero flag is set if the result of the last arithme- tic or logical operation was equal to zero; other- wise it is cleared. switching between the three sets of flags is per- formed automatically when an nmi, an interrupt or a reti instructions occurs. as the nmi mode is automatically selected after the reset of the mcu, the st6 core uses at first the nmi flags. stack. the st6 cpu includes a true lifo hard- ware stack which eliminates the need for a stack pointer. the stack consists of six separate 12-bit ram locations that do not belong to the data space ram area. when a subroutine call (or inter- rupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the pc is shifted into the first level (the original contents of the sixth stack level are lost). when a subroutine or interrupt return occurs (ret or reti instructions), the first level register is shift- ed back into the pc and the value of each level is popped back into the previous level. since the ac- cumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. the stack will remain in its adeepesto position if more than 6 nested calls or interrupts are executed, and consequently the last return ad- dress will be lost. it will also remain in its highest position if the stack is empty and a ret or reti is executed. in this case the next instruction will be executed. figure 7. st6 cpu programming mode l short direct addressing mode vregister w register program counter six levels stack register cz normal flags interrupt flags nmi flags index register va000423 b7 b7 b7 b7 b7 b0 b0 b0 b0 b0 b0 b11 accumulator yreg.pointer xreg.pointer cz cz 16
18/72 st62t45b/e45b 3 clocks, reset, interrupts and power saving modes 3.1 clock system 3.1.1 main oscillator the mcu features a main oscillator which can be driven by an external clock, or used in conjunction with an at-cut parallel resonant crystal or a suita- ble ceramic resonator. figure 8 illustrates various possible oscillator con- figurations using an external crystal or ceramic res- onator, an external clock input. c l1 an c l2 should have a capacitance in the range 12 to 22 pf for an oscillator frequency in the 4-8 mhz range. the internal mcu clock frequency (f int ) is divid- ed by 13 to drive the cpu core and by 12 to drive the a/d converter and the watchdog timer, while clock used to drive on-chip peripherals depends on the peripheral as shown in the clock circuit block diagram. with an 8mhz oscillator frequency, the fastest machine cycle is therefore 1.625 m s. a machine cycle is the smallest unit of time needed to execute any operation (for instance, to increment the program counter). an instruction may require two, four, or five machine cycles for execution. figure 8. oscillator configurations figure 9. clock circuit block diagram osc in osc out c l1n c l2 st6xxx crystal/res onator clock osc in osc out st6xxx external clock nc va0016 va0015a main oscillator core :13 :12 timer 1 & 2 watchdog por f int adc oscin oscout f osc f int osc32in osc32out 32khz oscillator mux lcd controller driver eocr bit 5 (start /stop) 17
19/72 st62t45b/e45b clock system (cont'd) 3.1.2 32khz stand-by oscillator an additional 32khz stand-by on chip oscillator al- lows to generate real time interrupts and to supply the clock to the lcd driver with the main oscillator stopped. this enables the mcu to perform real time functions with the lcd display running while keeping advantages of low power consumption. figure 10 shows the 32khz oscillator block dia- gram. a 32.768khz quartz crystal must be connected to the osc32in and osc32out pins to perform the real time clock operation. two external capacitors of 15-22pf each must be connected between the oscillator pins and ground. the 32khz oscillator is managed by the dedicated status/control register 32ocr. as long as the 32khz stand-by oscillator is ena- bled, 32khz internal clock is available to drive lcd controller driver. this clock is divide by 2 14 to generate interrupt request every 500ms . the pe- riodic interrupt request serves as reference time- base for real time functions. note : when the 32khz stand-by oscillator is stopped (bit 5 of the status/control register cleared) the divider chain is supplied with a clock signal synchronous with machine cycle (f int /13), this produces an interrupt request every 13x2 14 clock cycle (i.e. 26.624ms) with an 8mhz quartz crystal. 32khz oscillator register (32ocr) address: dbh - read/write bit 7 = eosci . enable oscillator interrupt .this bit, when set, enables the 32khz oscillator inter- rupt request. bit 6 = osceoc . oscillator interrupt flag . this bit indicates when the 32khz oscillator has measured a 500ms elapsed time (providing a 32.768khzquartz crystal is connected to the 32khz oscillator dedicated pins). an interrupt re- quest can be generated in relation to the state of eosci bit. this bit must be cleared by the user program before leaving the interrupt service rou- tine. bit 5 = start/stop .o scillator start/stop bit . this bit, when set, enables the 32khz stand-by os- cillator and the free running divider chain is sup- plied by the 32khz oscillator signal. when this bit is cleared to zero the divider chain is supplied with f int /13. this register is cleared during reset. note : to achieve minimum power consumption in stop mode (no system clock), the stand-by oscillator must be switched off (real time function not availa- ble) by clearing the start/stop bit in the oscillator status/control register. figure 10. 32khz oscillator block diagram 70 eosci osceoc s/s d4 d3 d2 d1 d0 osc32khz eosci osceoc start stop x x xxx int osc32in osc32out 2x15...22pf 32.768khz crystal f int /13 osc32khz mux 1 0 div 2 14 18
20/72 st62t45b/e45b 3.2 resets the mcu can be reset in three ways: by the external reset input being pulled low; by power-on reset; by the digital watchdog peripheral timing out. 3.2.1 reset input the reset pin may be connected to a device of the application board in order to reset the mcu if required. the reset pin may be pulled low in run, wait or stop mode. this input can be used to reset the mcu internal state and ensure a correct start-up procedure. the pin is active low and features a schmitt trigger input. the internal reset signal is generated by adding a delay to the external signal. therefore even short pulses on the reset pin are acceptable, provided v dd has completed its rising phase and that the oscillator is running correctly (normal run or wait modes). the mcu is kept in the reset state as long as the reset pin is held low. if reset activation occurs in the run or wait modes, processing of the user program is stopped (run mode only), the inputs and outputs are con- figured as inputs with pull-up resistors and the main oscillator is restarted. when the level on the reset pin then goes high, the initialization se- quence is executed following expiry of the internal delay period. if reset pin activation occurs in the stop mode, the oscillator starts up and all inputs and outputs are configured as inputs with pull-up resistors. when the level of the reset pin then goes high, the initialization sequence is executed following expiry of the internal delay period. 3.2.2 power-on reset the function of the por circuit consists in waking up the mcu at an appropriate stage during the power-on sequence. at the beginning of this se- quence, the mcu is configured in the reset state: all i/o ports are configured as inputs with pull-up resistors and no instruction is executed. when the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. the initialization sequence is executed immedi- ately following the internal delay. the internal delay is generated by an on-chip coun- ter. the internal reset line is released 2048 internal clock cycles after release of the external reset. notes: to ensure correct start-up, the user should take care that the reset signal is not released before the v dd level is sufficient to allow mcu operation at the chosen frequency (see recommended op- erating conditions). a proper reset signal for a slow rising v dd supply can generally be provided by an external rc net- work connected to thereset pin. figure 11. reset and interrupt processing int latch cleared nmi mask set reset ( if present ) select nmi mode flags is reset still present? yes put ffeh on address bus from reset locations ffe/fff no fetch instruction load pc va000427 19
21/72 st62t45b/e45b resets (cont'd) 3.2.3 watchdog reset the mcu provides a watchdog timer function in order to ensure graceful recovery from software upsets. if the watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. this, amongst oth- er things, resets the watchdog counter. the mcu restarts just as though the reset had been generated by the reset pin, including the built-in stabilisation delay period. 3.2.4 application notes no external resistor is required between v dd and the reset pin, thanks to the built-in pull-up device. the por circuit operates dynamically, in that it triggers mcu initialization on detecting the rising edge of v dd . the typical threshold is in the region of 2 volts, but the actual value of the detected threshold depends on the way in which v dd rises. the por circuit is not designed to supervise static, or slowly rising or falling v dd . 3.2.5 mcu initialization sequence when a reset occurs the stack is reset, the pc is loaded with the address of the reset vector (lo- cated in program rom starting at address 0ffeh). a jump to the beginning of the user pro- gram must be coded at this address. following a reset, the interrupt flag is automatically set, so that the cpu is in non maskable interrupt mode; this prevents the initialisation routine from being interrupted. the initialisation routine should there- fore be terminated by a reti instruction, in order to revert to normal mode and enable interrupts. if no pending interrupt is present at the end of the in- itialisation routine, the mcu will continue by processing the instruction immediately following the reti instruction. if, however, a pending inter- rupt is present, it will be serviced. figure 12. reset and interrupt processing figure 13. reset block diagram reset reset vector jp jp:2 bytes/4 cycles reti reti: 1 byte/2 cycles initializat ion routine va00181 v dd reset 300k w 2.8k w power watc hdog reset ck counte r reset st6 internal reset f osc reset on reset va0200b 20
22/72 st62t45b/e45b resets (cont'd) table 6. register reset status register address(es) status comment eeprom control register port data registers port a,b direction register port a,b option register interrupt option register spi registers lcd mode control register 32khz oscillator register 0dfh 0c0h, 0c2h, 0c3h 0c4h to 0c5h 0cch, 0ceh 0c8h 0c2h to 0ddh 0dch 0dbh 00h eeprom enabled i/o are input with pull-up interrupt disabled spi disabled lcd display off interrupt disabled port c direction register port c option register 0c6h 0cfh ffh lcd output x, y, v, w, register accumulator data ram data ram page register data rom window register eeprom a/d result register 080h to 083h 0ffh 084h to 0bfh 0cbh 0c9h 00h to 03fh 0d0h undefined as written if programmed timer 1 status/control timer 1 counter register timer 1 prescaler register timer 2 status/control timer 2 counter register timer 2 prescaler register watchdog counter register a/d control register 0d4h 0d3h 0d2h 0d7h 0d5h 0d6h 0d8h 0d1h 00h ffh 7fh 00h ffh 7fh feh 40h timer 1 disabled/max count loaded timer 2 disabled/max count loaded a/d in standby 21
23/72 st62t45b/e45b 3.3 digital watchdog the digital watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. the watchdog circuit generates a reset when the downcounter reaches zero. user software can prevent this reset by reloading the counter, and should therefore be written so that the counter is regularly reloaded while the user program runs correctly. in the event of a software mishap (usu- ally caused by externally generated interference), the user program will no longer behave in its usual fashion and the timer register will thus not be re- loaded periodically. consequently the timer will decrement down to 00h and reset the mcu. in or- der to maximise the effectiveness of the watch- dog function, user software must be written with this concept in mind. watchdog behaviour is governed by one option, known as awatchdog activationo (i.e. hardware or software) (seetable 7). in the software option, the watchdog is disa- bled until bit c of the dwdr register has been set. when the watchdog is disabled, low power stop mode is available. once activated, the watchdog cannot be disabled, except by resetting the mcu. in the hardware option, the watchdog is per- manently enabled. since the oscillator will run continuously, low power mode is not available. the stop instruction is interpreted as a wait in- struction, and the watchdog continues to count- down. when the mcu exits stop mode (i.e. when an in- terrupt is generated), the watchdog resumes its activity. table 7. recommended option choices functions required recommended optio ns stop mode asoftware watchdogo watchdog ahardware watchdogo 22
24/72 st62t45b/e45b digital watchdog (cont'd) the watchdog is associated with a data space register (digital watchdog register, dwdr, loca- tion 0d8h) which is described in greater detail in section 3.3.1 digital watchdog register (dwdr) . this register is set to 0feh on reset: bit c is cleared to a0o, which disables the watchdog; the timer downcounter bits, t0 to t5, and the sr bit are all set to a1o, thus selecting the longest watch- dog timer period. this time period can be set to the user's requirements by setting the appropriate value for bits t0 to t5 in the dwdr register. the sr bit must be set to a1o, since it is this bit which generates the reset signal when it changes to a0o; clearing this bit would generate an immediate re- set. it should be noted that the order of the bits in the dwdr register is inverted with respect to the as- sociated bits in the down counter: bit 7 of the dwdr register corresponds, in fact, to t0 and bit 2 to t5. the user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this regis- ter. the relationship between the dwdr register bits and the physical implementation of the watch- dog timer downcounter is illustrated infigure 14. only the 6 most significant bits may be used to de- fine the time period, since it is bit 6 which triggers the reset when it changes to a0o. this offers the user a choice of 64 timed periods ranging from 3,072 to 196,608 clock cycles (with an oscillator frequency of 8mhz, this is equivalent to timer pe- riods ranging from 384 m s to 24.576ms). figure 14. watchdog counter control watchdog control register d0 d1 d3 d4 d5 d6 d7 watchdog counter c sr t5 t4 t3 t2 t1 d2 t0 osc 12 reset vr02068a 2 8 23
25/72 st62t45b/e45b digital watchdog (cont'd) 3.3.1 digital watchdog register (dwdr) address: 0d8h e read/write reset status: 1111 1110b bit 0 = c : watchdog control bit if the hardware option is selected, this bit is forced high and the user cannot change it (the watchdog is always active). when the software option is se- lected, the watchdog function is activated by set- ting bit c to 1, and cannot then be disabled (save by resetting the mcu). when c is kept low the counter can be used as a 7-bit timer. this bit is cleared to a0o on reset. bit 1 = sr : software reset bit this bit triggers a reset when cleared. when c = a0o (watchdog disabled) it is the msb of the 7-bit timer. this bit is set to a1o on reset. bits 2-7 = t5-t0 : downcounter bits it should be noted that the register bits are re- versed and shifted with respect to the physical counter: bit-7 (t0) is the lsb of the watchdog downcounter and bit-2 (t5) is the msb. these bits are set to a1o on reset. 3.3.2 application notes the watchdog plays an important supporting role in the high noise immunity of st62xx devices, and should be used wherever possible. watchdog re- lated options should be selected on the basis of a trade-off between application security and stop mode availability. when stop mode is not required, hardware acti- vation should be preferred, as it provides maxi- mum security, especially during power-on. when software activation is selected and the watchdog is not activated, the downcounter may be used as a simple 7-bit timer (remember that the bits are in reverse order). the software activation option should be chosen only when the watchdog counter is to be used as a timer. to ensure the watchdog has not been un- expectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, wd, #+3 ldi wd, 0fdh 70 t0 t1 t2 t3 t4 t5 sr c 24
26/72 st62t45b/e45b digital watchdog (cont'd) these instructions test the c bit and reset the mcu (i.e. disable the watchdog) if the bit is set (i.e. if the watchdog is active), thus disabling the watchdog. in all modes, a minimum of 28 instructions are ex- ecuted after activation, before the watchdog can generate a reset. consequently, user software should load the watchdog counter within the first 27 instructions following watchdog activation (software mode), or within the first 27 instructions executed following a reset (hardware activation). it should be noted that when the gen bit is low (in- terrupts disabled), the nmi interrupt is active but cannot cause a wake up from stop/wait modes. figure 15. digital watchdog block diagram rsff 8 data bus va00010 -2 -12 oscillator reset write reset db0 r s q db1.7 set load 7 8 -2 set clock 25
27/72 st62t45b/e45b 3.4 interrupts the cpu can manage four maskable interrupt sources, in addition to a non maskable interrupt source (top priority interrupt). each source is as- sociated with a specific interrupt vector which contains a jump instruction to the associated in- terrupt service routine. these vectors are located in program space (see table 8). when an interrupt source generates an interrupt request, and interrupt processing is enabled, the pc register is loaded with the address of the inter- rupt vector (i.e. of the jump instruction), which then causes a jump to the relevant interrupt serv- ice routine, thus servicing the interrupt. interrupt sources are linked to events either on ex- ternal pins, or on chip peripherals. several events can be ored on the same interrupt source, and relevant flags are available to determine which event triggered the interrupt. the non maskable interrupt request has the high- est priority and can interrupt any interrupt routine at any time; the other four interrupts cannot inter- rupt each other. if more than one interrupt request is pending, these are processed by the processor core according to their priority level: source #1 has the higher priority while source #4 the lower. the priority of each interrupt source is fixed. table 8. interrupt vector map 3.4.1 interrupt request all interrupt sources but the non maskable inter- rupt source can be disabled by setting accordingly the gen bit of the interrupt option register (ior). this gen bit also defines if an interrupt source, in- cluding the non maskable interrupt source, can restart the mcu from stop/wait modes. interrupt request from the non maskable interrupt source #0 is latched by a flip flop which is auto- matically reset by the core at the beginning of the non-maskable interrupt service routine. interrupt request from source #1 can be config- ured either as edge or level sensitive by setting accordingly the les bit of the interrupt option register (ior). interrupt request from source #2 are always edge sensitive. the edge polarity can be configured by setting accordingly the esb bit of the interrupt op- tion register (ior). interrupt request from sources #3 & #4 are level sensitive. in edge sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. so, the occurrence of an interrupt can be stored, until completion of the running interrupt routine be- fore being processed. if several interrupt requests occurs before completion of the running interrupt routine, only the first request is stored. storage of interrupt requests is not available in level sensitive mode. to be taken into account, the low level must be present on the interrupt pin when the mcu samples the line after instruction execution. at the end of every instruction, the mcu tests the interrupt lines: if there is an interrupt request the next instruction is not executed and the appropri- ate interrupt service routine is executed instead. table 9. interrupt option register description interrupt source priority vector address interrupt source #0 1 (ffch-ffdh) interrupt source #1 2 (ff6h-ff7h) interrupt source #2 3 (ff4h-ff5h) interrupt source #3 4 (ff2h-ff3h) interrupt source #4 5 (ff0h-ff1h) gen set enable all interrupts cleared disable all interrupts esb set rising edge mode on inter- rupt source #2 cleared falling edge mode on inter- rupt source #2 les set level-sensitive mode on in- terrupt source #1 cleared falling edge mode on inter- rupt source #1 others not used 26
28/72 st62t45b/e45b iinterrupts (cont'd) 3.4.2 interrupt procedure the interrupt procedure is very similar to a call procedure, indeed the user can consider the inter- rupt as an asynchronous call procedure. as this is an asynchronous event, the user cannot know the context and the time at which it occurred. as a re- sult, the user should save all data space registers which may be used within the interrupt routines. there are separate sets of processor flags for nor- mal, interrupt and non-maskable interrupt modes, which are automatically switched and so do not need to be saved. the following list summarizes the interrupt proce- dure: mcu the interrupt is detected. the c and z flags are replaced by the interrupt flags (or by the nmi flags). the pc contents are stored in the first level of the stack. the normal interrupt lines are inhibited (nmi still active). the first internal latch is cleared. the associated interrupt vector is loaded in thepc. warning: in some circumstances, when a maskable interrupt occurs while the st6 core is in normal mode and especially during the execu- tion of an oldi ior, 00ho instruction (disabling all maskable interrupts): if the interrupt arrives during the first 3 cycles of the oldio instruction (which is a 4-cycle instruction) the core will switch to interrupt mode but the flags cn and zn will not switch to the interrupt pair ci and zi. user user selected registers are saved within the in- terrupt service routine (normally on a software stack). the source of the interrupt is found by polling the interrupt flags (if more than one source is asso- ciated with the same vector). the interrupt is serviced. return from interrupt (reti) mcu automatically the mcu switches back to the nor- mal flag set (or the interrupt flag set) and pops the previous pc value from the stack. the interrupt routine usually begins by the identi- fying the device which generated the interrupt re- quest (by polling). the user should save the regis- ters which are used within the interrupt routine in a software stack. after the reti instruction is exe- cuted, the mcu returns to the main routine. figure 16. interrupt processing flow chart ins truc tion fetch in stru ction exec ute ins truct ion was the in stru ction areti ? ? clear inter ru pt mask select program flags opopo the stac ked pc ? c hec k if ther e is an in terru pt re quest an d int er ru pt mask select inte rn al mode flag push the pc into the stack load pc from in terr upt vec tor (ffc/ ffd) set interr up t mask no no yes is the cor e already in nor mal mod e? va000014 yes no yes 27
29/72 st62t45b/e45b iinterrupts (cont'd) 3.4.3 interrupt option register (ior) the interrupt option register (ior) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. this register is write-only and cannot be accessed by single-bit operations. address: 0c8h e write only reset status: 00h bit 7, bits 3-0 = unused . bit 6 = les : level/edge selection bit . when this bit is set to one, the interrupt source #1 is level sensitive. when cleared to zero the edge sensitive mode for interrupt request is selected. bit 5 = esb : edge selection bit . the bit esb selects the polarity of the interrupt source #2. bit 4 = gen : global enable interrupt . when this bit is set to one, all interrupts are enabled. when this bit is cleared to zero all the interrupts (exclud- ing nmi) are disabled. when the gen bit is low, the nmi interrupt is ac- tive but cannot cause a wake up from stop/wait modes. this register is cleared on reset. 3.4.4 interrupt sources interrupt sources available on the ST62E45B/t45b are summarized in thefigure 10 with associated mask bit to enable/disable the in- terrupt request. table 10. interrupt requests and mask bits 70 - les esb gen - - - - peripheral register address register mask bit masked interrupt source interrupt source general ior c8h gen all interrupts, excluding nm i all timer 1 timer 2 tscr1 tscr2 d4h d7h eti tmz: timer overflow source 3 a/d converter adcr d1h eai eoc: end of conversion source 4 spi spi c2h all end of transmission source 1 port pan orpa-drpa c0h-c4h orpan-drpan pan pin source 2 port pbn orpb-drpb c1h-c5h orpbn-drpbn pbn pin source 2 port pcn orpc-drpc c6h-cfh orpcn-drpcn pcn pin source 2 32khz osc 32ocr dbh eosci osceoc source 3 28
30/72 st62t45b/e45b interrupts (cont'd) figure 17. interrupt block diagram port a pbe v dd from register port a,b,c single bit enable ff clk q clr i 0 start int #0 nmi (ffc ,d)) int #2 (ff4,5) nmi port b bits spi ff clk q clr 0 mux 1 i 1 start ior bit 6 (les) pbe ff clk q clr ior bit 5 (esb) i 2 start int #1 (ff6,7) int #3 (ff2,3) int #4 (ff0,1) ior bit 4(gen) port c tmz eti tmz eti osceoc eosci eai eoc resta rt stop/wait from pbe timer1 timer2 osc32khz a/d converter 29
31/72 st62t45b/e45b 3.5 power saving modes the wait and stop modes have been imple- mented in the st62xx family of mcus in order to reduce the product's electrical consumption dur- ing idle periods. these two power saving modes are described in the following paragraphs. 3.5.1 wait mode the mcu goes into wait mode as soon as the wait instruction is executed. the microcontroller can be considered as being in a asoftware frozeno state where the core stops processing the pro- gram instructions, the ram contents and periph- eral registers are preserved as long as the power supply voltage is higher than the ram retention voltage. in this mode the peripherals are still ac- tive. wait mode can be used when the user wants to reduce the mcu power consumption during idle periods, while not losing track of time or the capa- bility of monitoring external events. the active os- cillator is not stopped in order to provide a clock signal to the peripherals. timer counting may be enabled as well as the timer interrupt, before en- tering the wait mode: this allows the wait mode to be exited when a timer interrupt occurs. the same applies to other peripherals which use the clock signal. if the wait mode is exited due to a reset (either by activating the external pin or generated by the watchdog), the mcu enters a normal reset proce- dure. if an interrupt is generated during wait mode, the mcu's behaviour depends on the state of the processor core prior to the wait instruction, but also on the kind of interrupt request which is generated. this is described in the following para- graphs. the processor core does not generate a delay following the occurrence of the interrupt, be- cause the oscillator clock is still available and no stabilisation period is necessary. 3.5.2 stop mode if the watchdog is disabled, stop mode is avail- able. when in stop mode, the mcu is placed in the lowest power consumption mode. in this oper- ating mode, the microcontroller can be considered as being afrozeno, no instruction is executed, the oscillator is stopped, the ram contents and pe- ripheral registers are preserved as long as the power supply voltage is higher than the ram re- tention voltage, and the st62xx core waits for the occurrence of an external interrupt request or a reset to exit the stop state. if the stop state is exited due to a reset (by ac- tivating the external pin) the mcu will enter a nor- mal reset procedure. behaviour in response to in- terrupts depends on the state of the processor core prior to issuing the stop instruction, and also on the kind of interrupt request that is gener- ated. this case will be described in the following para- graphs. the processor core generates a delay af- ter occurrence of the interrupt request, in order to wait for complete stabilisation of the oscillator, be- fore executing the first instruction. 30
32/72 st62t45b/e45b power saving mode (cont'd) 3.5.3 exit from wait and stop modes the following paragraphs describe how the mcu exits from wait and stop modes, when an inter- rupt occurs (not a reset). it should be noted that the restart sequence depends on the original state of the mcu (normal, interrupt or non-maskable in- terrupt mode) prior to entering wait or stop mode, as well as on the interrupt type. interrupts do not affect the oscillator selection. 3.5.3.1 normal mode if the mcu was in the main routine when the wait or stop instruction was executed, exit from stop or wait mode will occur as soon as an interrupt oc- curs; the related interrupt routine is executed and, on completion, the instruction which follows the stop or wait instruction is then executed, pro- viding no other interrupts are pending. 3.5.3.2 non maskable interrupt mode if the stop or wait instruction has been execut- ed during execution of the non-maskable interrupt routine, the mcu exits from the stop or wait mode as soon as an interrupt occurs: the instruction which follows the stop or wait instruction is ex- ecuted, and the mcu remains in non-maskable in- terrupt mode, even if another interrupt has been generated. 3.5.3.3 normal interrupt mode if the mcu was in interrupt mode before the stop or wait instruction was executed, it exits from stop or wait mode as soon as an interrupt oc- curs. nevertheless, two cases must be consid- ered: if the interrupt is a normal one, the interrupt rou- tine in which the wait or stop mode was en- tered will be completed, starting with the execution of the instruction which follows the stop or the wait instruction, and the mcu is still in the interrupt mode. at the end of this rou- tine pending interrupts will be serviced in ac- cordance with their priority. in the event of a non-maskable interrupt, the non-maskable interrupt service routine is proc- essed first, then the routine in which the wait or stop mode was entered will be completed by executing the instruction following the stop or wait instruction. the mcu remains in normal interrupt mode. notes: to achieve the lowest power consumption during run or wait modes, the user program must take care of: configuring unused i/os as inputs without pull-up (these should be externally tied to well defined logic levels); placing all peripherals in their power down modes before entering stop mode; when the hardware activated watchdog is select- ed, or when the software watchdog is enabled, the stop instruction is disabled and a wait in- struction will be executed in its place. if all interrupt sources are disabled (gen low), the mcu can only be restarted by a reset. although setting gen low does not mask the nmi as an in- terrupt, it will stop it generating a wake-up signal. the wait and stop instructions are not execut- ed if an enabled interrupt request is pending. 31
33/72 st62t45b/e45b 4 on-chip peripherals 4.1 i/o ports the mcu features input/output lines which may be individually programmed as any of the follow- ing input or output configurations: input without pull-up or interrupt input with pull-up and interrupt input with pull-up, but without interrupt analog input push-pull output open drain output the lines are organised as bytewise ports. each port is associated with 3 registers in data space. each bit of these registers is associated with a particular line (for instance, bits 0 of port a data, direction and option registers are associat- ed with the pa0 line of port a). the data registers (drx), are used to read the voltage level values of the lines which have been configured as inputs, or to write the logic value of the signal to be output on the lines configured as outputs. the port data registers can be read to get the effective logic levels of the pins, but they can be also written by user software, in conjunction with the related option registers, to select the dif- ferent input mode options. single-bit operations on i/o registers are possible but care is necessary because reading in input mode is done from i/o pins while writing will direct- ly affect the port data register causing an unde- sired change of the input configuration. the data direction registers (ddrx) allow the data direction (input or output) of each pin to be set. the option registers (orx) are used to select the different port options available both in input and in output mode. all i/o registers can be read or written to just as any other ram location in data space, so no extra ram cells are needed for port data storage and manipulation. during mcu initialization, all i/o registers are cleared and the input mode with pull- ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts. figure 18. i/o port block diagram v dd reset s in controls s out shif t register data data direction register register option register input/output to inter rupt v dd to adc va00413 32
34/72 st62t45b/e45b i/o ports (cont'd) 4.1.1 operating modes each pin may be individually programmed as input or output with various configurations. this is achieved by writing the relevant bit in the data (dr), data direction (ddr) and option reg- isters (or). table 11 illustrates the various port configurations which can be selected by user soft- ware. 4.1.1.1 input options pull-up, high impedance option. all input lines can be individually programmed with or without an internal pull-up by programming the or and dr registers accordingly. if the pull-up option is not selected, the input pin will be in the high-imped- ance state. 4.1.1.2 interrupt options all input lines can be individually connected by software to the interrupt system by programming the or and dr registers accordingly. the inter- rupt trigger modes (falling edge, rising edge and low level) can be configured by software as de- scribed in the interrupt chapter for each port. 4.1.1.3 analog input options some pins can be configured as analog inputs by programming the or and dr registers according- ly. these analog inputs are connected to the on- chip 8-bit analog to digital converter. only one pin should be programmed as an analog input at any time, since by selecting more than one input simultaneously their pins will be effectively short- ed. table 11. i/o port option selection note: x = don't care ddr or dr mode option 0 0 0 input with pull-up, no interrupt 0 0 1 input no pull-up, no interrupt 0 1 0 input with pull-up and with interrupt 0 1 1 input analog input (when available) 1 0 x output open-drain output (20ma sink when available) 1 1 x output push-pull output (20ma sink when available) 33
35/72 st62t45b/e45b i/o ports (cont'd) 4.1.2 safe i/o state switching sequence switching the i/o ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. the recom- mended safe transitions are illustrated in figure 19. all other transitions are potentially risky and should be avoided when changing the i/o operat- ing mode, as it is most likely that undesirable side- effects will be experienced, such as spurious inter- rupt generation or two pins shorted together by the analog multiplexer. single bit instructions (set, res, inc and dec) should be used with great caution on ports data registers, since these instructions make an implicit read and write back of the entire register. in port input mode, however, the data register reads from the input pins directly, and not from the data regis- ter latches. since data register information in input mode is used to set the characteristics of the input pin (interrupt, pull-up, analog input), these may be unintentionally reprogrammed depending on the state of the input pins. as a general rule, it is better to limit the use of single bit instructions on data registers to when the whole (8-bit) port is in output mode. in the case of inputs or of mixed inputs and outputs, it is advisable to keep a copy of the data register in ram. single bit instructions may then be used on the ram copy, after which the whole copy register can be written to the port data regis- ter: set bit, datacopy ld a, datacopy ld dra, a care must also be taken to not use inc or dec in- structions on a port register when the 8 bits are not available on the devices. the wait and stop instructions allow the st62xx to be used in situations where low power consumption is needed. the lowest power con- sumption is achieved by configuring i/os in input mode with well-defined logic levels. the user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion. figure 19. diagram showing safe i/o state transitions note *. xxx = ddr, or, dr bits respectively interrupt pull-up output open drain output push-pull input pull-up (reset state) input analog output open drain output push-pull input 010* 000 100 110 011 001 101 111 34
36/72 st62t45b/e45b i/o ports (cont'd) table 12. i/o port configuration for the st62t45b/e45b note 1 . provided the correct configuration has been selected. mode available on (1) schematic input pa5-pa7 pb0-pb7 pc0-pc7 input with pull up (reset state except for pc0-pc7) pa5-pa7 pb0-pb7 pc0-pc7 input with pull up with interrupt pa5-pa7 pb0-pb7 pc0-pc7 analog input pa5-pa7 pb0-pb3 open drain output 5ma open drain output 20ma pa5-pa7 pb0-pb7 pc0-pc7 (1ma) pb4-pb7 push-pull output 5ma push-pull output 20ma pa5-pa7 pb0-pb7 pc0-pc7 (1ma) pb4-pb7 data in interrupt data in interrupt data in interrupt data out adc data out 35
37/72 st62t45b/e45b i/o ports (cont'd) 4.1.3 lcd alternate functions (combiports) pc0 to pc7 can also be individually defined as 8 lcd segment output by setting ddrc, orc and drc registers as shown infigure 13. on the contrary with other i/o lines, the reset state is the lcd output mode. these 8 segment lines are recognised as s33..s40 by the embedded lcd controller drive. 4.1.4 spi alternate functions pb6/sin and pb5/scl pins must be configured as input through the ddr and or registers to be used data in and data clock (slave mode) for the spi. all input modes are available and i/o's can be read independantly of the spi at any time. pb7/sout must be configured in open drain output mode to be used as data out for the spi. in output mode, the value present on the pin is the port data register content only if pb7 is defined as push pull output, while serial transmission is possible only in open drain mode. table 13. pc0-pc7 combiport option selection note: x = don't care figure 20. peripheral interface configuration of spi ddr or dr mode option 0 0 0 input with pull-up, no interrupt 0 0 1 input no pull-up, no interrupt 0 1 0 input with pull-up and with interrupt 0 1 1 input lcd segment (reset state) 1 0 x output open-drain output 1 1 x output push-pull output pb7/sout pb6/sin pb5/scl pid opr dr 1 mux 0 out in synchronous serial i/o clock pid dr pid dr pp/od vr01661f 36
38/72 st62t45b/e45b i/o ports (cont'd) 4.1.5 i/o port option registers ora/b/c (cch pa, cdh pb, cfh pc) read/write bit 7-0 = px7 - px0 : port a, b, c option register bits. 4.1.6 i/o port data direction registers ddra/b/c (c4h pa, c5h pb, c6h pc) read/write bit 7-0 = px7 - px0 : port a, b, c data direction registers bits. 4.1.7 i/o port data registers dra/b/c (c0h pa, c1h pb, c3h pc) read/write bit 7-0 = px7 - px0 : port a, b, c data registers bits. 70 px7 px6 px5 px4 px3 px2 px1 px0 70 px7 px6 px5 px4 px3 px2 px1 px0 70 px7 px6 px5 px4 px3 px2 px1 px0 37
39/72 st62t45b/e45b 4.2 timer 1 & 2 the mcu features two on-chip timer peripheral named timer 1 & timer 2. each of these timers consist of an 8-bit counter with a 7-bit programma- ble prescaler, giving a maximum count of 2 15 . figure 22 and figure 23 show the timer block di- agrams. an external timer pin is available to the user on the timer 1 allowing external control of the counting clock or signal generation. the content of the 8-bit counter can be read/writ- ten in the timer/counter register, tcr, while the state of the 7-bit prescaler can be read in the psc register. the control logic device is managed in the tscr register as described in the following paragraphs. the 8-bit counter is decremented by the output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program control. when it decrements to zero then the tmz (timer zero) bit in the tscr is set to a1o. if the eti (ena- ble timer interrupt) bit in the tscr is also set to a1o, an interrupt request is generated as described in the interrupt chapter. the timer interrupt can be used to exit the mcu from wait mode. the prescaler input can be either the internal fre- quency f int divided by 12 (timer 1 & 2) or an ex- ternal clock applied to the timer pin (timer 1). the prescaler decrements on the rising edge. de- pending on the division factor programmed by ps2, ps1 and ps0 bits in the tscr. the clock in- put of the timer/counter register is multiplexed to different sources. for division factor 1, the clock input of the prescaler is also that of timer/counter; for factor 2, bit 0 of the prescaler register is con- nected to the clock input of tcr. this bit changes its state at half the frequency of the prescaler input clock. for factor 4, bit 1 of the psc is connected to the clock input of tcr, and so forth. the prescaler initialize bit, psi, in the tscr register must be set to a1o to allow the prescaler (and hence the coun- ter) to start. if it is cleared to a0o, all the prescaler bits are set to a1o and the counter is inhibited from counting. the prescaler can be loaded with any value between 0 and 7fh, if bit psi is set to a1o. the prescaler tap is selected by means of the ps2/ps1/ps0 bits in the control register. figure 21 illustrates the timer's working principle. figure 21. timer working principle bit0 bit1 bit2 bit3 bit6 bit5 bit4 clock 7-bit prescaler 8-1 multiplexer 8-bit counter bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1 0 2 34 5 67 ps0 ps1 ps2 va00186 38
40/72 st62t45b/e45b figure 22. timer 1 block diagram figure 23. timer 2 block diagram databus 8 8 8 8 8-bit counter 6 5 4 3 2 1 0 psc status/control register b7 b6 b5 b4 b3 b2 b1 b0 tmz eti tout dout psi ps2 ps1 ps0 select 1of8 3 latch synchronization logic timer interrupt line va00009 status/control 8 tmz eti d5 d4 psi ps2 ps1 ps0 register 8-bit 1of8 select interrupt line / 3 5 6 4 3 2 1 0 psc vr02070a f int b7 b6 b5 b4 b3 b2 b1 b0 88 . 12 data bus . 39
41/72 st62t45b/e45b timer 1& 2 (cont'd) 4.2.1 timer 1 operating modes there are three operating modes, which are se- lected by the tout and dout bits (see tscr register). these three modes correspond to the two clocks which can be connected to the 7-bit prescaler (f int 12 or timer pin signal), and to the output mode. 4.2.1.1 gated mode (tout = a0o, dout = a1o) in this mode the prescaler is decremented by the timer clock input (f int 12), but only when the signal on the timer pin is held high (allowing pulse width measurement). this mode is selected by clearing the tout bit in the tscr register to a0o (i.e. as input) and setting the dout bit to a1o. 4.2.1.2 event counter mode (tout = a0o, dout = a0o) in this mode, the timer pin is an input and the prescaler is decremented on the rising edge. 4.2.1.3 output mode (tout = a1o, dout = data out) the timer pin is connected to the dout latch, hence the timer prescaler is clocked by the pres- caler clock input (f int 12). the user can select the desired prescaler division ratio through the ps2, ps1, ps0 bits. when the tcr count reaches 0, it sets the tmz bit in the tscr. the tmz bit can be tested under program control to perform a timer function whenever it goes high. the low-to-high tmz bit transition is used to latch the dout bit of the tscr and trans- fer it to the timer pin. this operating mode allows external signal generation on the timer pin. table 14. timer operating modes 4.2.2 timer 2 operating mode the timer prescaler is clocked by the prescaler clock input (f int 12). the user can select the desired prescaler division ratio through the ps2, ps1, ps0 bits. when the tcr count reaches 0, it sets the tmz bit in the tscr. the tmz bit can be tested under program control to perform a timer function whenever it goes high. 4.2.3 timer interrupt when one of the counter registers decrements to zero with the associated eti (enable timer inter- rupt) bit set to one, an interrupt request is generat- ed as described in interrupt chapter. when the counter decrements to zero, the associated tmz bit in the tscr register is set to one. 4.2.4 application notes the user can select the presence of an on-chip pull-up on the timer pin as option. tmz is set when the counter reaches zero; how- ever, it may also be set by writing 00h in the tcr register or by setting bit 7 of the tscr register. the tmz bit must be cleared by user software when servicing the timer interrupt to avoid unde- sired interrupts when leaving the interrupt service routine. after reset, the 8-bit counter register is loaded with 0ffh, while the 7-bit prescaler is load- ed with 07fh, and the tscr register is cleared. this means that the timer is stopped (psi=a0o) and the timer interrupt is disabled. a write to the tcr register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a tcr register decrement to 00h occur simultaneously, the write will take precedence, and the tmz bit is not set until the 8-bit counter reaches 00h again. the values of the tcr and the psc registers can be read accurately at any time. tout dout timer pin timer function 0 0 input event counter 0 1 input gated input 1 0 output output a0o 1 1 output output a1o 40
42/72 st62t45b/e45b timer 1& 2 (cont'd) 4.2.5 timer 1 registers timer status control register (tscr) address: 0d4h e read/write bit 7 = tmz : timer zero bit a low-to-high transition indicates that the timer count register has decrement to zero. this bit must be cleared by user software before starting a new count. bit 6 = eti : enable timer interrup when set, enables the timer interrupt request. if eti=0 the timer interrupt is disabled. if eti=1 and tmz=1 an interrupt request is generated. bit 5 = tout : timer output control. when low, this bit select the input mode for the timer pin. when high the output mode is select- ed. bit 4 = dout: data ouput data sent to the timer output when tmz is set high (output mode only). input mode selection (input mode only) bit 3 = psi : prescaler initialize bit used to initialize the prescaler and inhibit its counting. when psi=a0o the prescaler is set to 7fh and the counter is inhibited. when psi=a1o the prescaler is enabled to count downwards. as long as psi=a0o both counter and prescaler are not running. bit 2, 1, 0 = ps2, ps1, ps0 : prescaler mux. se- lect. these bits select the division ratio of the pres- caler register. table 15. prescaler division factors timer counter register (tcr) address: 0d3h e read/write bit 7-0 = d7-d0 : counter bits. prescaler register psc address: 0d2h e read/write bit 7 = d7 : always read as o0o. bit 6-0 = d6-d0 : prescaler bits. 70 tmz eti tout dout psi ps2 ps1 ps0 ps2 ps1 ps0 divided by 0001 0012 0104 0118 10016 10132 11064 111128 70 d7 d6 d5 d4 d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 41
43/72 st62t45b/e45b timer 1& 2 (cont'd) 4.2.6 timer 2 registers timer status control register (tscr) address: 0d7h e read/write bit 7 = tmz : timer zero bit a low-to-high transition indicates that the timer count register has decrement to zero. this bit must be cleared by user software before starting a new count. bit 6 = eti : enable timer interrup when set, enables the timer interrupt request. if eti=0 the timer interrupt is disabled. if eti=1 and tmz=1 an interrupt request is generated. bit 5 = d5 : reserved must be set to a1o. bit 4 = d4 do not care. bit 3 = psi : prescaler initialize bit used to initialize the prescaler and inhibit its counting. when psi=a0o the prescaler is set to 7fh and the counter is inhibited. when psi=a1o the prescaler is enabled to count downwards. as long as psi=a0o both counter and prescaler are not running. bit 2, 1, 0 = ps2, ps1, ps0 : prescaler mux. se- lect. these bits select the division ratio of the pres- caler register. table 16. prescaler division factors timer counter register (tcr) address: 0d6h e read/write bit 7-0 = d7-d0 : counter bits. prescaler register psc address: 0d5h e read/write bit 7 = d7 : always read as o0o. bit 6-0 = d6-d0 : prescaler bits. 70 tmz eti d5 d4 psi ps2 ps1 ps0 ps2 ps1 ps0 divided by 0001 0012 0104 0118 10016 10132 11064 111128 70 d7 d6 d5 d4 d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 42
44/72 st62t45b/e45b 4.3 a/d converter (adc) the a/d converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate i/o functions (the number of which is device de- pendent), offering 8-bit resolution with a typical conversion time of 70us (at an oscillator clock fre- quency of 8mhz). the adc converts the input voltage by a process of successive approximations, using a clock fre- quency derived from the oscillator with a division factor of twelve. with an oscillator clock frequency less than 1.2mhz, conversion accuracy is de- creased. selection of the input pin is done by configuring the related i/o line as an analog input via the op- tion and data registers (refer to i/o ports descrip- tion for additional information). only one i/o line must be configured as an analog input at any time. the user must avoid any situation in which more than one i/o pin is selected as an analog input si- multaneously, to avoid device malfunction. the adc uses two registers in the data space: the adc data conversion register, adr, which stores the conversion result, and the adc control regis- ter, adcr, used to program the adc functions. a conversion is started by writing a a1o to the start bit (sta) in the adc control register. this auto- matically clears (resets to a0o) the end of conver- sion bit (eoc). when a conversion is complete, the eoc bit is automatically set to a1o, in order to flag that conversion is complete and that the data in the adc data conversion register is valid. each conversion has to be separately initiated by writing to the sta bit. the sta bit is continuously scanned so that, if the user sets it to a1o while a previous conversion is in progress, a new conversion is started before com- pleting the previous one. the start bit (sta) is a write only bit, any attempt to read it will show a log- ical a0o. the a/d converter features a maskable interrupt associated with the end of conversion. this inter- rupt is associated with interrupt vector #4 and oc- curs when the eoc bit is set (i.e. when a conver- sion is completed). the interrupt is masked using the eai (interrupt mask) bit in the control register. the power consumption of the device can be re- duced by turning off the adc peripheral. this is done by setting the pds bit in the adc control register to a0o. if pds=a1o, the a/d is powered and enabled for conversion. this bit must be set at least one instruction before the beginning of the conversion to allow stabilisation of the a/d con- verter. this action is also needed before entering wait mode, since the a/d comparator is not auto- matically disabled in wait mode. during reset, any conversion in progress is stopped, the control register is reset to 40h and the adc interrupt is masked (eai=0). figure 24. adc block diagram 4.3.1 application notes the a/d converter does not feature a sample and hold circuit. the analog voltage to be measured should therefore be stable during the entire con- version cycle. voltage variation should not exceed 1/2 lsb for the optimum conversion accuracy. a low pass filter may be used at the analog input pins to reduce input voltage variation during con- version. when selected as an analog channel, the input pin is internally connected to a capacitor c ad of typi- cally 12pf. for maximum accuracy, this capacitor must be fully charged at the beginning of conver- sion. in the worst case, conversion starts one in- struction (6.5 m s) after the channel has been se- lected. in worst case conditions, the impedance, asi, of the analog voltage source is calculated us- ing the following formula: 6.5 m s=9xc ad xasi (capacitor charged to over 99.9%), i.e. 30 k w in- cluding a 50% guardband. asi can be higher if c ad has been charged for a longer period by add- ing instructions before the start of conversion (adding more than 26 cpu cycles is pointless). control register converter va00418 result register reset interrupt clock av av dd ain 8 core control signals ss 8 core 43
45/72 st62t45b/e45b a/d converter (cont'd) since the adc is on the same chip as the micro- processor, the user should not switch heavily loaded output signals during conversion, if high precision is required. such switching will affect the supply voltages used as analog references. the accuracy of the conversion depends on the quality of the power supplies (v dd and v ss ). the user must take special care to ensure a well regu- lated reference voltage is present on the v dd and v ss pins (power supply voltage variations must be less than 5v/ms). this implies, in particular, that a suitable decoupling capacitor is used at the v dd pin. the converter resolution is given by:: the input voltage (ain) which is to be converted must be constant for 1 m s before conversion and remain constant during conversion. conversion resolution can be improved if the pow- er supply voltage (v dd ) to the microcontroller is lowered. in order to optimise conversion resolution, the user can configure the microcontroller in wait mode, because this mode minimises noise distur- bances and power supply variations due to output switching. nevertheless, the wait instruction should be executed as soon as possible after the beginning of the conversion, because execution of the wait instruction may cause a small variation of the v dd voltage. the negative effect of this var- iation is minimized at the beginning of the conver- sion when the converter is less sensitive, rather than at the end of conversion, when the less sig- nificant bits are determined. the best configuration, from an accuracy stand- point, is wait mode with the timer stopped. in- deed, only the adc peripheral and the oscillator are then still working. the mcu must be woken up from wait mode by the adc interrupt at the end of the conversion. it should be noted that waking up the microcontroller could also be done using the timer interrupt, but in this case the timer will be working and the resulting noise could affect conversion accuracy. a/d converter control register (adcr) address: 0d1h e read/write bit 7 = eai : enable a/d interrupt. if this bit is set to a1o the a/d interrupt is enabled, when eai=0 the interrupt is disabled. bit 6 = eoc : end of conversion. read only .this read only bit indicates when a conversion has been completed. this bit is automatically reset to a0o when the sta bit is written. if the user is using the interrupt option then this bit can be used as an interrupt pending bit. data in the data conversion register are valid only when this bit is set to a1o. bit 5 = sta : start of conversion. write only . writ- ing a a1o to this bit will start a conversion on the se- lected channel and automatically reset to a0o the eoc bit. if the bit is set again when a conversion is in progress, the present conversion is stopped and a new one will take place. this bit is write on- ly, any attempt to read it will show a logical zero. bit 4 = pds : power down selection. this bit acti- vates the a/d converter if set to a1o. writing a a0o to this bit will put the adc in power down mode (idle mode). bit 3-0 = d3-d0. not used a/d converter data register (adr) address: 0d0h e read only bit 7-0 = d7-d0 : 8 bit a/d conversion result. v dd v ss 256 ---------------------------- 70 eai eoc sta pds d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 44
46/72 st62t45b/e45b 4.4 serial peripheral interface (spi) the on-chip spi is an optimized serial synchro- nous interface that supports a wide range of in- dustry standard spi specifications. the on-chip spi is controlled by small and simple user soft- ware to perform serial data exchange. the serial shift clock can be implemented either by software (using the bit-set and bit-reset instructions), with the on-chip timer 1 by externally connecting the spi clock pin to the timer pin or by directly apply- ing an external clock to the scl line. the peripheral is composed by an 8-bit data/shift register and a 4-bit binary counter while the sin pin is the serial shift input and sout is the serial shift output. these two lines can be tied together to implement two wires protocols (i c-b us, etc). when data is serialized, the msb is the first bit. sin has to be programmed as input. for serial out- put operation sout has to be programmed as open-drain output. the scl, sin and sout spi clock and data signals are connected to 3 i/o lines on the same external pins. with these 3 lines, the spi can operate in the following operating modes: software spi, s-bus, i c-bu s and as a standard serial i/o (clock, data, enable). an interrupt request can be generated af- ter eight clock pulses. figure 25 shows the spi block diagram. the scl line clocks, on the falling edge, the shift register and the counter. to allow spi operation in slave mode, the scl pin must be programmed as input and an external clock must be supplied to this pin to drive the spi peripheral. in master mode, scl is programmed as output, a clock signal must be generated by software to set and reset the port line. figure 25. spi block diagram set res clk reset 4-bit counter (q4=high after clock8) data reg direction i/o port 8-bit data shift register reset load dout output enable 8-bit tristate data i/o reset i/o port i/o port cp cp din d0............... .............d7 to processor data bus q4 q4 opr reg. din scl sin sout spi interrupt disable register spi data register data reg direction data reg direction dout write read mux 0 1 interrupt vr01504 45
47/72 st62t45b/e45b serial peripheral interface (cont'd) after 8 clock pulses (d7..d0) the output q4 of the 4-bit binary counter becomes low, disabling the clock from the counter and the data/shift register. q4 enables the clock to generate an interrupt on the 8th clock falling edge as long as no reset of the counter (processor write into the 8-bit data/shift register) takes place. after a processor reset the interrupt is disabled. the interrupt is active when writing data in the shift register and desactivated when writing any data in the spi interrupt disable register. the generation of an interrupt to the core pro- vides information that new data is available (input mode) or that transmission is completed (output mode), allowing the core to generate an acknowl- edge on the 9th clock pulse (i c-b us). the interrupt is initiated by a high to low transition, and therefore interrupt options must be set ac- cordingly as defined in the interrupt section. after power on reset, or after writing the data/shift register, the counter is reset to zero and the clock is enabled. in this condition the data shift register is ready for reception. no start condition has to be detected. through the user software the core may pull down the sin line (acknowledge) and slow down the scl, as long as it is needed to carry out data from the shift register. i c-bus master-slave, receiver-transmitter when pins sin and sout are externally connected together it is possible to use the spi as a receiver as well as a transmitter. through software routine (by using bit-set and bit-reset on i/o line) a clock can be generated allowing i c-bu s to work in mas- ter mode. when implementing an i c-b us protocol, the start condition can be detected by setting the processor into a wait for start condition by enabling the inter- rupt of the i/o port used for the sin line. this frees the processor from polling the sin and scl lines. after the transmission/reception the processor has to poll for the stop condition. in slave mode the user software can slow down the scl clock frequency by simply putting the scl i/o line in output open-drain mode and writ- ing a zero into the corresponding data register bit. as it is possible to directly read the sin pin directly through the port register, the software can detect a difference between internal data and external data (master mode). similar condition can be applied to the clock. three (four) wire serial bus it is possible to use a single general purpose i/o pin (with the corresponding interrupt enabled) as a chip enable pin. scl acts as active or passive clock pin, sin as data in and sout as data out (four wire bus). sin and sout can be connected togeth- er externally to implement three wire bus. note : when the spi is not used, the three i/o lines (sin, scl, sout) can be used as normal i/o, with the following limitation: bit sout cannot be used in open drain mode as this enables the shift register output to the port. it is recommended, in order to avoid spurious in- terrupts from the spi, to disable the spi interrupt (the default state after reset) i.e. no write must be made to the 8-bit shift register. an explicit interrupt disable may be made in software by a dummy write to the spi interrupt disable register. spi data/shift register address: ddh - read/write (sdsr) a write into this register enables spi interrupt after 8 clock pulses. spi interrupt disable register address: c2h - read/write (sidr) a dummy write to this register disables spi inter- rupt. 70 d7 d6 d5 d4 d3 d2 d1 d0 70 d7 d6 d5 d4 d3 d2 d1 d0 46
48/72 st62t45b/e45b 4.5 lcd controller-driver on-chip lcd driver includes all features required for lcd driving, including multiplexing of the com- mon plates. multiplexing allows to increase dis- play capability without increasing the number of segment outputs. in that case, the display capabil- ity is equal to the product of the number of com- mon plates with the number of segment outputs. a dedicated lcd ram is used to store the pattern to be displayed while control logic generates ac- cordingly all the waveforms sent onto the segment or common outputs. segments voltage supply is mcu supply independant, and included driving stages allow direct connection to the lcd panel. the multiplexing ratio (number of common plates) and the base lcd frame frequency is software configurable to achieve the best trade-off con- trast/display capability for each display panel. the 32khz clock used for the lcd controller is derivated from the mcu's internal clock and there- fore does not require a dedicated oscillator. the division factor is set by the three bits hf0..hf2 of the lcd mode control register lcdcr as sum- marized in table 17 for recommanded oscillator quartz values. in case of oscillator failure, all seg- ment and common lines are switched to ground to avoid any dc biasing of the lcd elements. table 17. oscillator selection bits notes : 1. the usage f osc values different from those defined in this table cause the lcd to operate at a reference frequency different from 32.768khz, ac- cording to division factor of table 17. 2. it is not recommended to select an internal frequency lower than 32.768khz as the clock su- pervisor circuit may switch off the lcd peripheral if lower frequency is detected. figure 26. lcd block diagram mcu oscillator f osc hf2 hf1 hf0 division factor 0 0 0 clock disabled: display off 1.048mhz 0 1 1 32 2.097mhz 1 0 0 64 4.194mhz 1 0 1 128 8.388mhz 1 1 0 256 data bus control register lcd ram segment driver common drive r voltage divide r controller clock selection vlcd 1/3 2/3 vlcd vlcd backplan es segments f int osc 32khz (when available) vr02099 32khz 47
49/72 st62t45b/e45b lcd controller-driver (continued) 4.5.1 multiplexing ratio and frame frequency setting up to 4 common plates com1..com4 can be used for multiplexing ratio ranging from 1/1 to 1/4. the selection is made by the bits ds0 and ds1 of the lcdcr as shown in thetable 18. table 18. multiplexing ratio if the 1/1 multiplexing ratio is chosen, lcd seg- ments are refreshed with a frame frequency flcd derived from 32khz clock with a division ratio de- fined by the bits lf0..lf2 of the lcdcr. when a higher multiplexing ratio is set, refreshment frequency is decreased accordingly ( table 19). table 19. lcd frame frequency selection 4.5.2 segment and common plates driving lcd panels physical structure requires precise timings and stepped voltage values on common and segment outputs. timings are managed by the lcd controller, while voltages are derivated from the vlcd value through internal resistive di- vision. this internal divider is disabled when the lcd driver is off in order to avoid consumption on vlcd pin. the 1/3 vlcd and 2/3 vlcd values used in 1/1, 1/3 and 1/4 multiplexing ratio modes are internally generated and issued on external pins, while 1/2 vlcd value used in 1/2 mode is obtained by ex- ternal connection of the 1/3vlcd and 2/3vlcd pins (figure 27). figure 27. bias config for 1/2 duty figure 28. typical current consumption on vlcd pin (25 c, no load, flcd=512hz, mux=1/3-1/4) note : for display voltages v lcd < 4.5v the resis- tivity of the divider may be too high for some appli- cations (especially using 1/3 or 1/4 duty display mode). in that case an external resistive divider must be used to achieve the desired resistivity. ds1 ds0 display mode active backplanes 0 0 1/4 mux.ratio com1, 2, 3, 4 0 1 1/1 mux.ratio com1 1 0 1/2 mux.ratio com1, 2 1 1 1/3 mux.ratio com1, 2, 3 lf2 lf1 lf0 base f lcd (hz) frame frequency f f (hz) 1/1 mux. ratio 1/2 mux. ratio 1/3 mux. ratio 1/4 mux. ratio 0 0 0 64 64 32 21 16 0 0 1 85 85 43 28 21 0 1 0 128 128 64 43 32 0 1 1 171 171 85 57 43 1 0 0 256 256 128 85 64 1 0 1 341 341 171 114 85 1 1 0 512 512 256 171 128 1 1 1 reserved v lcd v lcd1/3 v ss v lcd2/3 r h r h r h lcdoff vr01367 i lcd ( m a) v lcd (v) 70 60 50 40 30 20 10 34567 8910 vr01838 48
50/72 st62t45b/e45b lcd controller-driver (continued) figure 29. typical network to connect to v lcd pins if vlcd 4.5v typical external resistances values are in the range of 100 k w to 150 k w . external capacitances in the range of 10 to 47 nf can be added to v lcd 2/3 and v lcd 1/3 pins and to v lcd if the v lcd con- nection is highly impedant. 4.5.3 lcd ram lcd ram is organised as a lcd panel with a ma- trix architecture. each bit of its content is logically mapped to a physical element of the display panel addressed by a couple (segment;common). if a bit is set, the relevant element of the lcd matrix is turned-on. on the contrary, an element remains turned-off as long the associated bit within the lcd ram is kept cleared. after a reset, the lcd ram is not initialised and contain arbitrary information. if the choosen multiplexing ratio does not use some common plates, corresponding ram ad- dresses are free for general purpose data storage. figure 30. addressing map of the lcd ram v lcd r v lcd1/3 v ss v lcd2/3 c r: 100k w r r c c: 47nf vr01840 ram address msb lsb e0 e1 e2 e3 e4 e5 s8 s16 s24 s32 s40 s48 s7 s15 s23 s31 s39 s47 s6 s14 s22 s30 s38 s46 s5 s13 s21 s29 s37 s45 s4 s12 s20 s28 s36 s44 na s11 s19 s27 s35 s43 na s10 s18 s26 s34 s42 na s9 s17 s25 s33 s41 com1 e6 e7 e8 e9 ea eb s8 s16 s24 s32 s40 s48 s7 s15 s23 s31 s39 s47 s6 s14 s22 s30 s38 s46 s5 s13 s21 s29 s37 s45 s4 s12 s20 s28 s36 s44 na s11 s19 s27 s35 s43 na s10 s18 s26 s34 s42 na s9 s17 s25 s33 s41 com2 ec ed ee ef f0 f1 s8 s16 s24 s32 s40 s48 s7 s15 s23 s31 s39 s47 s6 s14 s22 s30 s38 s46 s5 s13 s21 s29 s37 s45 s4 s12 s20 s28 s36 s44 na s11 s19 s27 s35 s43 na s10 s18 s26 s34 s42 na s9 s17 s25 s33 s41 com3 f2 f3 f4 f5 f6 f7 s8 s16 s24 s32 s40 s48 s7 s15 s23 s31 s39 s47 s6 s14 s22 s30 s38 s46 s5 s13 s21 s29 s37 s45 s4 s12 s20 s28 s36 s44 na s11 s19 s27 s35 s43 na s10 s18 s26 s34 s42 na s9 s17 s25 s33 s41 com4 49
51/72 st62t45b/e45b lcd controller-driver (continued) 4.5.4 stand by or stop operation mode no clock from the main oscillator is available in stop mode for the lcd controller, and the con- troller is switched off when the stop instruction is executed. all segment and common lines are then switched to ground to avoid any dc biasing of the lcd elements. operation in stop mode remain possible by switching to the osc32khz, by setting the hf0..hf2 bit of lcdcr accordingly (table 20). care must be taken for the oscillator switching that lcd function change is only effective at the end of a frame. therefore it must be guaranteed that enough clock pulses are delivered before entering into stop mode. otherwise the lcd function is switched off at stop instruction execution. table 20. oscillator source selection 4.5.5 lcd mode control register (lcdcr) address: dch - read/write bits 7-6 = ds0, ds1. multiplexing ratio select bits . these bits select the number of common back- planes used by the lcd control. bits 5-3 = hf0, hf1, hf2 . oscillator select bits . these bits allow the lcd controller to be supplied with the correct frequency when different high main oscillator frequencies are selected as sys- tem clock. table 17 shows the set-up for different clock crystals. bits 2-0 = lf0, lf1, lf2 . base frame frequency select bits. these bits control the lcd base oper- ational frequency of the lcd common lines. lf0, lf1, lf2 define the 32khz division factor as shown in table 21 table 21. 32khz division factor for base frequency selection hf2 hf1 hf0 division factor 0 0 0 clock disabled: display off 0 0 1 auxiliary 32khz oscillator 0 1 0 reserved 1 1 1 reserved others division from mcu f int 70 ds1 ds0 hf2 hf1 hf0 lf2 lf1 lf0 lf2 lf1 lf0 32khz division factor 000512 001386 010256 011192 100128 10196 11064 1 1 1 reserved 50
52/72 st62t45b/e45b 5 software 5.1 st6 architecture the st6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. the st6 core has the ability to set or clear any register or ram location bit of the data space with a single instruction. furthermore, the program may branch to a selected address depending on the status of any bit of the data space. the carry bit is stored with the value of the bit when the set or res instruction is processed. 5.2 addressing modes the st6 core offers nine addressing modes, which are described in the following paragraphs. three different address spaces are available: pro- gram space, data space, and stack space. pro- gram space contains the instructions which are to be executed, plus the data for immediate mode in- structions. data space contains the accumulator, the x,y,v and w registers, peripheral and in- put/output registers, the ram locations and data rom locations (for storage of tables and con- stants). stack space contains six 12-bit ram cells used to stack the return addresses for subroutines and interrupts. immediate . in the immediate addressing mode, the operand of the instruction follows the opcode location. as the operand is a rom byte, the imme- diate addressing mode is used to access con- stants which do not change during program exe- cution (e.g., a constant used to initialize a loop counter). direct . in the direct addressing mode, the address of the byte which is processed by the instruction is stored in the location which follows the opcode. direct addressing allows the user to directly ad- dress the 256 bytes in data space memory with a single two-byte instruction. short direct . the core can address the four ram registers x,y,v,w (locations 80h, 81h, 82h, 83h) in the short-direct addressing mode. in this case, the instruction is only one byte and the selection of the location to be processed is contained in the opcode. short direct addressing is a subset of the direct addressing mode. (note that 80h and 81h are also indirect registers). extended . in the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant bits of the opcode with the byte following the op- code. the instructions (jp, call) which use the extended addressing mode are able to branch to any address of the 4k bytes program space. an extended addressing mode instruction is two- byte long. program counter relative . the relative ad- dressing mode is only used in conditional branch instructions. the instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations around the address of the relative instruction. if the condition is not true, the instruction which follows the relative instruc- tion is executed. the relative addressing mode in- struction is one-byte long. the opcode is obtained in adding the three most significant bits which characterize the kind of the test, one bit which de- termines whether the branch is a forward (when it is 0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to fh) which must be added or sub- tracted to the address of the relative instruction to obtain the address of the branch. bit direct . in the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the ad- dress of the byte in which the specified bit must be set or cleared. thus, any bit in the 256 locations of data space memory can be set or cleared. bit test & branch . the bit test and branch ad- dressing mode is a combination of direct address- ing and relative addressing. the bit test and branch instruction is three-byte long. the bit iden- tification and the tested condition are included in the opcode byte. the address of the byte to be tested follows immediately the opcode in the pro- gram space. the third byte is the jump displace- ment, which is in the range of -127 to +128. this displacement can be determined using a label, which is converted by the assembler. indirect . in the indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed by the content of one of the indirect registers, x or y (80h,81h). the indirect register is selected by the bit 4 of the opcode. a register indirect instruction is one byte long. inherent . in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. these instructions are one byte long. 51
53/72 st62t45b/e45b 5.3 instruction set the st6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. they can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, jump/call, and bit manipulation. the following par- agraphs describe the different types. all the instructions belonging to a given type are presented in individual tables. load & store . these instructions use one, two or three bytes in relation with the addressing mode. one operand is the accumulator for load and the other operand is obtained from data memory us- ing one of the addressing modes. for load immediate one operand can be any of the 256 data space bytes while the other is always immediate data. table 22. load & store instructions notes: x,y. indirect register pointers, v & w short direct registers # . immediate data (stored in rom memory) rr. data space register d . affected * . not affected instruction addressing mode bytes cycles flags zc ld a, x short direct 1 4 d * ld a, y short direct 1 4 d * ld a, v short direct 1 4 d * ld a, w short direct 1 4 d * ld x, a short direct 1 4 d * ld y, a short direct 1 4 d * ld v, a short direct 1 4 d * ld w, a short direct 1 4 d * ld a, rr direct 2 4 d * ld rr, a direct 2 4 d * ld a, (x) indirect 1 4 d * ld a, (y) indirect 1 4 d * ld (x), a indirect 1 4 d * ld (y), a indirect 1 4 d * ldi a, #n immediate 2 4 d * ldi rr, #n immediate 3 4 * * 52
54/72 st62t45b/e45b instruction set (cont'd) arithmetic and logic . these instructions are used to perform the arithmetic calculations and logic operations. in and, add, cp, sub instruc- tions one operand is always the accumulator while the other can be either a data space memory con- tent or an immediate value in relation with the ad- dressing mode. in clr, dec, inc instructions the operand can be any of the 256 data space ad- dresses. in com, rlc, sla the operand is al- ways the accumulator. table 23. arithmetic & logic instructions notes: x,y.indirect register pointers, v & w short direct registersd. affected # . immediate data (stored in rom memory)* . not affected rr. data space register instruction addressing mode bytes cycles flags zc add a, (x) indirect 1 4 dd add a, (y) indirect 1 4 dd add a, rr direct 2 4 dd addi a, #n immediate 2 4 dd and a, (x) indirect 1 4 dd and a, (y) indirect 1 4 dd and a, rr direct 2 4 dd andi a, #n immediate 2 4 dd clr a short direct 2 4 dd clr r direct 3 4 * * com a inherent 1 4 dd cp a, (x) indirect 1 4 dd cp a, (y) indirect 1 4 dd cp a, rr direct 2 4 dd cpi a, #n immediate 2 4 dd dec x short direct 1 4 d * dec y short direct 1 4 d * dec v short direct 1 4 d * dec w short direct 1 4 d * dec a direct 2 4 d * dec rr direct 2 4 d * dec (x) indirect 1 4 d * dec (y) indirect 1 4 d * inc x short direct 1 4 d * inc y short direct 1 4 d * inc v short direct 1 4 d * inc w short direct 1 4 d * inc a direct 2 4 d * inc rr direct 2 4 d * inc (x) indirect 1 4 d * inc (y) indirect 1 4 d * rlc a inherent 1 4 dd sla a inherent 2 4 dd sub a, (x) indirect 1 4 dd sub a, (y) indirect 1 4 dd sub a, rr direct 2 4 dd subi a, #n immediate 2 4 dd 53
55/72 st62t45b/e45b instruction set (cont'd) conditional branch . the branch instructions achieve a branch in the program when the select- ed condition is met. bit manipulation instructions . these instruc- tions can handle any bit in data space memory. one group either sets or clears. the other group (see conditional branch) performs the bit test branch operations. control instructions . the control instructions control the mcu operations during program exe- cution. jump and call. these two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space. table 24. conditional branch instructions notes : b. 3-bit address rr. data space register e. 5 bit signed displacement in the range -15 to +16 d . affected. the tested bit is shifted into carry. ee. 8 bit signed displacement in the range -126 to +129 * . not affected table 25. bit manipulation instructions notes: b. 3-bit address; * . not affected rr. data space register; table 26. control instructions notes: 1. this instruction is deactivatedand a wai t is automatically executed instead of a stop if the watchdog function is selected. d . affected *. not affected table 27. jump & call instructions notes: abc. 12-bit address; * . not affected instruction branch if bytes cycles flags zc jrc e c = 1 1 2 * * jrnc e c = 0 1 2 * * jrze z=1 1 2 * * jrnz e z = 0 1 2 * * jrr b, rr, ee bit = 0 3 5 * d jrs b, rr, ee bit = 1 3 5 * d instruction addressing mode bytes cycles flags zc set b,rr bit direct 2 4 * * res b,rr bit direct 2 4 * * instruction addressing mode bytes cycles flags zc nop inherent 1 2 * * ret inherent 1 2 * * reti inherent 1 2 dd stop (1) inherent 1 2 * * wait inherent 1 2 * * instruction addressing mode bytes cycles flags zc call abc extended 2 4 * * jp abc extended 2 4 * * 54
56/72 st62t45b/e45b opcode map summary. the following table contains an opcode map for the instructions used by the st6 low 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 low hi hi 0 0000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 0 0000 e abc e b0,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 0001 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 ldi 1 0001 e abc e b0,rr,ee e x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 2 0010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 cp 2 0010 e abc e b4,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 3 0011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 cpi 3 0011 e abc e b4,rr,ee e a,x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 4 0100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 add 4 0100 e abc e b2,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 5 0101 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 addi 5 0101 e abc e b2,rr,ee e y e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 6 0110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 inc 6 0110 e abc e b6,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 7 0111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 7 0111 e abc e b6,rr,ee e a,y e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 8 1000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr,ee e # e (x),a 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 9 1001 e abc e b1,rr,ee e v e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc a 1010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 and a 1010 e abc e b5,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind b 1011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 andi b 1011 e abc e b5,rr,ee e a,v e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm c 1100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 sub c 1100 e abc e b3,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind d 1101 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 subi d 1101 e abc e b3,rr,ee e w e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm e 1110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 dec e 1110 e abc e b7,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind f 1111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc f 1111 e abc e b7,rr,ee e a,w e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc abbreviation s for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1 prc mnemonic addressing mode bytes cycle operand 55
57/72 st62t45b/e45b opcode map summary (continued) low 8 1000 9 1001 a 1010 b 1011 c 1100 d 1101 e 1110 f 1111 low hi hi 0 0000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 ldi 2 jrc 4 ld 0 0000 e abc e b0,rr e rr,nn e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind 1 0001 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 1 0001 e abc e b0,rr e x e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 2 0010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 com 2 jrc 4 cp 2 0010 e abc e b4,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 3 0011 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 cp 3 0011 e abc e b4,rr e x,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 4 0100 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 reti 2 jrc 4 add 4 0100 e abc e b2,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 5 0101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 add 5 0101 e abc e b2,rr e y e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 6 0110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 stop 2 jrc 4 inc 6 0110 e abc e b6,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 7 0111 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 inc 7 0111 e abc e b6,rr e y,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 8 1000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr e # e (y),a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 9 1001 2 rnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 9 1001 e abc e b1,rr e v e rr,a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir a 1010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 rcl 2 jrc 4 and a 1010 e abc e b5,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind b 1011 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 and b 1011 e abc e b5,rr e v,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir c 1100 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 ret 2 jrc 4 sub c 1100 e abc e b3,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind d 1101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 sub d 1101 e abc e b3,rr e w e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir e 1110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 wait 2 jrc 4 dec e 1110 e abc e b7,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind f 1111 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 dec f 1111 e abc e b7,rr e w,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir abbreviation s for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5 bit displacement imm immediate b 3 bit address inh inherent rr 1byte dataspace address ext extended nn 1 byte immediate data b.d bit direct abc 12 bit address bt bit test ee 8 bit displacement pcr program counter relative ind indirect 2 jrc e 1 prc mnemonic addressing mode bytes cycle operand 56
58/72 st62t45b/e45b 6 electrical characteristics 6.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations .the average chip-junc- tion temperature, tj, in celsius can be obtained from: tj= ta + pd x rthja where: ta = ambient temperature. rthja = package thermal resistance (junction-to ambient). pd = pint + pport. pint = idd x vdd (chip internal power). pport = port power dissipation (deter- mined by the user). notes: - stresses above those listed as oabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended period s may affect device reliability. - (1) within these limits, clamping diodes are guarantee to be not conductive. voltages outside these limits are authorised as long as injection current is kept within the specification. symbol parameter value unit v dd supply voltage -0.3 to 7.0 v v i input voltage v ss - 0.3 to v dd + 0.3 (1) v v o output voltage v ss - 0.3 to v dd + 0.3 (1) v i o current drain per pin excluding v dd ,v ss 10 ma iv dd total current into v dd (source) 50 ma iv ss total current out of v ss (sink) 50 ma tj junction temperature 150 c t stg storage temperature -60 to 150 c 57
59/72 st62t45b/e45b 6.2 recommended operating conditions notes : 1. care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the a/d conversion. for a -1ma injection, a maximum 10 k w is recommanded. 2. an oscillator frequency above 1mhz is recommended for reliable a/d results. figure 31. maximum operating frequency (fmax) versus supply voltage (v dd ) the shaded area is outside the recommended operating range; device functionality is not guaranteed under these conditions. symbol parameter test condition s value unit min. typ. max. t a operating temperature 6 suffix version 1 suffix version -40 0 85 70 c v dd operating supply voltage f osc = 4mhz fosc= 8mhz 3.0 4.5 6.0 6.0 v f osc oscillator frequency 2) v dd =3v v dd = 4.5v 0 0 4.0 8.0 mhz i inj+ pin injection current (positive) v dd = 4.5 to 5.5v +5 ma i inj- pin injection current (negative) v dd = 4.5 to 5.5v -5 ma 8 7 6 5 4 3 2 1 2.5 3 3.5 4 4.5 5 5.5 6 supply voltage (v dd ) maximum freque ncy (mhz) function ality is not guaranteed in this area 58
60/72 st62t45b/e45b 6.3 dc electrical characteristics (t a = -40 to +85 c unless otherwise specified) notes: (1) hysteresis voltage between switching levels (2) all peripherals running (3) all peripherals in stand-by symbol parameter test cond itions value unit min. typ. max. v il input low level voltage all input pins v dd x 0.3 v v ih input high level voltage all input pins v dd x 0.7 v v hys hysteresis voltage (1) all input pins v dd =5v v dd =3v 0.2 0.2 v v ol low level output voltage all output pins v dd = 5.0v; i ol =+10 m a v dd = 5.0v; i ol = + 5ma 0.1 0.8 v low level output voltage 20 ma sink i/o pins v dd = 5.0v; i ol =+10 m a v dd = 5.0v; i ol = +10ma v dd = 5.0v; i ol = +20ma 0.1 0.8 1.3 v oh high level output voltage all output pins v dd = 5.0v; i ol =-10 m a v dd = 5.0v; i ol = -5.0ma 4.9 3.5 v r pu pull-up resistance all input pins 40 100 200 kw reset pin 150 350 900 i il i ih input leakage current all input pins but reset v in =v ss (no pull-up configured) v in =v dd 0.1 1.0 m a input leakage current reset pin v in =v ss v in =v dd -8 -16 -30 10 i dd supply current in reset mode v reset =v ss f osc =8mhz 7ma supply current in run mode (2) v dd =5.0v f int =8mhz 7 ma supply current in wait mode (3) v dd =5.0v f int =8mhz 2 ma supply current in stop mode (3) i load =0ma v dd =5.0v 10 m a 59
61/72 st62t45b/e45b 6.4 ac electrical characteristics (t a = -40 to +85 c unless otherwise specified) notes : 1. period for which v dd has to be connected at 0v to allow internal reset function at next power-up. 6.5 a/d converter characteristics (t a = -40 to +85 c unless otherwise specified) notes : 1. noise at av dd ,av ss <10mv 2. wit h oscillator frequencies less than 1mhz, the a/d converter accuracy is decreased. . symbol parameter test conditions value unit min. typ. max. t rec supply recovery time (1) 100 ms t wr minimum pulse width (v dd = 5v) reset pin nmi pin 100 100 ns t wee eeprom write time t a =25 c t a =85 c 5 10 10 20 ms endurance eeprom write/erase cycle q a l ot acceptance 300,000 1 million cycles retention eeprom data retention t a =55 c 10 years c in input capacitance all inputs pins 10 pf c out output capacitance all outputs pins 10 pf symbol parameter test condi tions value unit min. typ. max. res resolution 8 bit a tot total accuracy (1) (2) f osc > 1.2mhz f osc > 32khz 2 4 lsb t c conversion time f osc =8mhz 70 m s zir zero input reading conversion result when v in =v ss 00 hex fsr full scale reading conversion result when v in =v dd ff hex ad i analog input current during conversion v dd = 4.5v 1.0 m a ac in analog input capacitance 2 5 pf 60
62/72 st62t45b/e45b 6.6 timer characteristics (t a = -40 to +85 c unless otherwise specified) note*: when available. 6.7 spi characteristics (t a = -40 to +85 c unless otherwise specified) 6.8 lcd electrical characteristics (t a = -40 to +85 c unless otherwise specified) notes : 1. the dc offset refers to all segment and common outputs. it is the difference between the measured voltage value and nominal valu e for every voltage level. 2. an external resistor network is required when vlcd is lower then 4.5v. 6.9 pss electrical characteristics (when available) (t a = -40 to +85 c unless otherwise specified symbol parameter test condi tions value unit min. typ. max. f in input frequency on timer pin* mhz t w pulse width at timer pin* v dd = 3.0v v dd > 4.5v 1 125 m s ns f int 8 ---------- symbol parameter test conditions value unit min. typ. max. f cl clock frequency applied on scl 1 mhz t su set-up time applied on sin 50 ns t h hold time applied onsin 100 ns symbol parameter test conditions value unit min. typ. max. v os dc offset voltage v lcd = vdd, no load 50 mv v oh com high level, output voltage seg high level, output voltage i=100 m a, v lcd =5v i=50 m a, v lcd =5v 4.5 v v ol com low level, output voltage seg low level, output voltage i=100 m a, v lcd =5v i=50 m a, v lcd =5v 0.5 v lcd display voltage see note 2 v dd -0.2 10 symbol parameter test conditions value unit min. typ. max. v pss pss pin input voltage vss v dd v i pss pss pin input current v pss =5.0v, t a =25 c pss running pss stopped 350 1 m a 61
63/72 st62t45b/e45b 7 general information 7.1 package mechanical data figure 32. 52-pin plastic quad flat package figure 33. 52-pin ceramic quad flat package with window dim mm inches min typ max min typ max a 3.40 0.134 a1 0.25 0.010 a2 2.55 2.80 3.05 0.100 0.110 0.120 b 0.35 0.50 0.014 0.020 c 0.13 0.23 0.005 0.009 d 16.95 17.20 17.45 0.667 0.677 0.687 d1 13.90 14.00 14.10 0.547 0.551 0.555 d3 12.00 0.472 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.00 0.472 e 1.00 0.039 k 0 7 0 7 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 m number of pins n 52 pqfp52 dim mm inches min typ max min typ max a 3.27 0.129 a1 0.50 0.020 b 0.35 0.40 0.50 0.014 0.016 0.020 c 0.13 0.15 0.23 0.005 0.006 0.009 d 16.65 17.20 17.75 0.656 0.677 0.699 d1 13.57 13.97 14.37 0.566 d2 13.06 13.46 13.86 0.514 0.530 0.546 d3 12.00 0.472 e 1.00 0.039 g 12.70 0.500 g2 0.96 0.038 l 0.35 0.80 0.014 0.031 8.31 0.327 number of pins n 52 cqfp052w 62
64/72 st62t45b/e45b general information (continued) 7.2 package thermal characteristic 7.3 ordering information table 28. otp/eprom version ordering information symbol parameter test conditions value unit min. typ. max. rthja thermal resistance pqfp52 70 c/w cqfp52w 70 sales type program memory (bytes) i/o temperature range package ST62E45Bg1 3884 (eprom) 11 to 19 0to70 c cqfp52w st62t45bq6 3884 (otp) -40 to 85 c pqfp52 63
march 1998 65/72 r rev. 2.3 st62p45b 8-bit fastrom mcu with lcd driver, eeprom and a/d converter n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +85 c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 128 bytes n data eeprom: 128 bytes n user programmable options n 19 i/o pins, fully programmable as: input with pull-up resistor input without pull-up resistor input with interrupt generation open-drain or push-pull output analog input lcd segments (8 combiport lines) n 4 i/o lines can sink up to 20ma to drive leds or triacs directly n two 8-bit timer/counter with 7-bit programmable prescaler n digital watchdog n 8-bit a/d converter with 7 analog inputs n 8-bit synchronous peripheral interface (spi) n lcd driver with 24 segment outputs, 4 backplane outputs and selectable multiplexing ratio. n 32khz oscillator for stand-by lcd operation n on-chip clock oscillator can be driven by quartz crystal or ceramic resonator n one external non-maskable interrupt n st6245-emu2 emulation and development system (connects to an ms-dos pc via a parallel port). device summary pqfp52 device rom (bytes) i/o pins st62p45b 3884 11 to 19 64
66/72 st62p45b 1 general description 1.1 introduction the st62p45b is the f actory a dvanced s ervice t echnique rom (fastrom) versions of st62t45b otp devices. it offers the same functionality as otp devices, selecting as fastrom options the options de- fined in the programmable option byte of the otp version. 1.2 ordering information the following section deals with the procedure for transfer of customer codes to sgs-thomson. 1.2.1 transfer of customer code customer code is made up of the rom contents and the list of the selected fastrom options. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to sgs- thomson using the correctly filled option list appended. 1.2.2 listing generation and verification when sgs-thomson receives the user's rom contents, a computer listing is generated from it. this listing refers exactly to the rom contents and options which will be used to produce the speci- fied mcu. the listing is then returned to the cus- tomer who must thoroughly check, complete, sign and return it to sgs-thomson. the signed list- ing forms a part of the contractual agreement for the production of the specific customer mcu. the sgs-thomson sales organization will be pleased to provide detailed information on con- tractual points. table 29. rom memory map for st62p45b table 30. fastrom version ordering information device address description 0000h-007fh 0080h-0f9h 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi vector reset vector sales type rom i/o temperature range package st62p45bq1/xxx st62p45bq6/xxx 3884 11 to 19 0 to +70 c -40 to 85 c pqfp52 65
67/72 st62p45b st62p45b fastrom microcontroller option list customer . . . ...................... address ......................... ......................... contact . . . ...................... phoneno ......................... reference . . . ...................... sgs-thomson microelectronics references device: [ ] st62p45b package: [ ] plastic quad flat package (tape & reel) temperature range: [ ] 0 cto+70 c []-40 cto+85 c watchdog selection: [ ] software activation [ ] hardware activation nmi pull-up selection: [ ] yes [ ] no timer pull-up selection: [ ] yes [ ] no readout protection: [ ] standard [ ] enabled comments : number of segments and backplanes used: supply operating range in the application: oscillator fequency in the application: notes . . . ...................... signature . . . ...................... date ......................... 66
68/72 st62p45b notes: 67
march 1998 69/72 r rev. 2.3 st6245b 8-bit rom mcu with lcd driver, eeprom and a/d converter n 3.0 to 6.0v supply operating range n 8 mhz maximum clock frequency n -40 to +85 c operating temperature range n run, wait and stop modes n 5 interrupt vectors n look-up table capability in program memory n data storage in program memory: user selectable size n data ram: 128 bytes n data eeprom: 128 bytes n user programmable options n 19 i/o pins, fully programmable as: input with pull-up resistor input without pull-up resistor input with interrupt generation open-drain or push-pull output analog input lcd segments (8 combiport lines) n 4 i/o lines can sink up to 20ma to drive leds or triacs directly n two 8-bit timer/counter with 7-bit programmable prescaler n digital watchdog n 8-bit a/d converter with 7 analog inputs n 8-bit synchronous peripheral interface (spi) n lcd driver with 24 segment outputs, 4 backplane outputs and selectable multiplexing ratio. n 32khz oscillator for stand-by lcd operation n on-chip clock oscillator can be driven by quartz crystal or ceramic resonator n one external non-maskable interrupt n st6245-emu2 emulation and development system (connects to an ms-dos pc via a parallel port). device summary pqfp52 device rom (bytes) i/o pins st6245b 3884 11 to 19 1
70/72 st6245b 1 general description 1.1 introduction the st6245b is mask programmed rom version of st62t45b otp devices. it offers the same functionality as otp devices, selecting as rom options the options defined in the programmable option byte of the otp version. figure 1. programming wave form 1.2 rom readout protection if the rom readout protection option is selected, a protection fuse can be blown to pre- vent any access to the program memory content. in case the user wants to blow this fuse, high volt- age must be applied on the test pin. figure 2. programming circuit note: zpd15 is used for overvoltage protection vr02001 0.5s min 15 10 5 14vtyp 100 s max t t 4ma typ 100ma 15 0 s typ max tes t test vr02003 protect zp d15 5v v ss v dd te s t 47 f m 100nf 100nf 15v 14v 1
71/72 st6245b st6245b microcontroller option list customer . . . ...................... address ......................... ......................... contact . . . ...................... phoneno ......................... reference . . . ...................... sgs-thomson microelectronics references device: [ ] st6245b package: [ ] plastic quad flat package (tape & reel) temperature range: [ ] 0 cto+70 c []-40 cto+85 c special marking: [ ] no [ ] yes o_ _ _ _ _ _ _ _ _ _ _ o authorized characters are letters, digits, '.', '-', '/' and spaces only. maximum character count: pqfp52: 10 watchdog selection: [ ] software activation [ ] hardware activation nmi pull-up selection: [ ] yes [ ] no timer pull-up selection: [ ] yes [ ] no rom readout protection: [ ] standard (fuse cannot be blown) [ ] enabled (fuse can be blown by the customer) note: no part is delivered with protected rom. the fuse must be blown for protection to be effective. comments : number of segments and backplanes used: supply operating range in the application: oscillator fequency in the application: notes . . . ...................... signature . . . ...................... date ......................... 1
72/72 st6245b 1.3 ordering information the following section deals with the procedure for transfer of customer codes to sgs-thomson. 1.3.1 transfer of customer code customer code is made up of the rom contents and the list of the selected mask options. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file gener- ated by the development tool. all unused bytes must be set to ffh. the selected mask options are communicated to sgs-thomson using the correctly filled op- tion list appended. 1.3.2 listing generation and verification when sgs-thomson receives the user's rom contents, a computer listing is generated from it. this listing refers exactly to the mask which will be used to produce the specified mcu. the listing is then returned to the customer who must thorough- ly check, complete, sign and return it to sgs-thomson. the signed listing forms a part of the contractual agreement for the creation of the specific customer mask. the sgs-thomson sales organization will be pleased to provide detailed information on con- tractual points. table 1. rom memory map for st6245b table 2. rom version ordering information information furnished is believed to be accurate and reliable. however, sgs-thomso n microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-th omson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-tho mson microelectronics. ? 1998 sgs-thomson microelectronics - all rights reserved. printed in france by imprimerie agl purchase of i 2 c components by sgs-th omson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomso n microelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. device address description 0000h-007fh 0080h-0f9h 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi vector reset vector sales type rom i/o temperature range package st6245bq1/xxx st6245bq6/xxx 3884 11 to 19 0 to +70 c -40 to 85 c pqfp52 1

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